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參數(shù)資料
| 型號： | EVAL-AD7923CB2 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP |
| 中文描述： | 4通道，200 kSPS的，12位序列ADC的16引腳TSSOP |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 430K |
| 代理商： | EVAL-AD7923CB2 |
AD7923
–17–
REV. 0
For example, if the AD7923 is operated in a continuous sam-
pling mode, with a throughput rate of 200 kSPS and an SCLK
of 20 MHz (AV
DD
= 5 V), and the device is placed in Auto
Shutdown Mode, i.e., if PM1 = 0 and PM0 = 1, then the power
consumption is calculated as follows:
The maximum power dissipation during conversion is 13.5 mW
(I
DD
= 2.7 mA max, AV
DD
= 5 V). If the power-up time from
Auto Shutdown is one dummy cycle, i.e., 1
m
s, and the remaining
conversion time is another cycle, i.e., 800 ns, then the AD7923
can be said to dissipate 13.5 mW for 1.8
m
s during each con-
version cycle. For the remainder of the conversion cycle, 3.2
m
s,
the part remains in Shutdown. The AD7923 can be said to
dissipate 2.5
m
W for the remaining 3.2
m
s of the conversion
cycle. If the throughput rate is 200 kSPS, the cycle time is
5
m
s and the average power dissipated during each cycle is
(1.8/5)
￥
(13.5 mW) + (3.2/5)
￥
(2.5
m
W) = 4.8616 mW.
Figure 15 shows the maximum power versus throughput rate
when using the Auto Shutdown Mode with 5 V and 3 V supplies.
THROUGHPUT – kSPS
10
0
200
P
0.1
0.01
80
1
100
140
180
20
40
60
120
160
AV
DD
= 5V
AV
DD
= 3V
Figure 15. Power vs. Throughput Rate
SERIAL INTERFACE
Figures 16 shows the detailed timing diagrams for serial inter-
facing to the AD7923. The serial clock provides the conversion
clock and controls the transfer of information to and from the
AD7923 during each conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode,
takes the bus out of three-state, and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require 16 SCLK cycles to complete. The track-and-hold
will go back into track on the 14th SCLK falling edge as shown
in Figure 16 at Point B. On the 16th SCLK falling edge the
DOUT line will go back into three-state. If the rising edge of
CS
occurs before 16 SCLKs have elapsed, the conversion will be
terminated and the DOUT line will go back into three-state and
the Control Register will not be updated; otherwise DOUT
returns to three-state on the 16th SCLK falling edge, as shown
in Figure 16.
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7923. For the AD7923,
the twelve bits of data are preceded by two leading zeros and
two channel address bits ADD1 and ADD0, identifying which
channel the result corresponds to.
CS
going low clocks out the
first leading zero to be read in by the microcontroller or DSP on
the first falling edge of SCLK. The first falling edge of SCLK
will also clock out the second leading zero to be read in by the
microcontroller or DSP on the second SCLK falling edge, and
so on. The remaining two address bits and 12-data bits are then
clocked out by subsequent SCLK falling edges beginning with
the first address bit ADD1, thus the second falling clock edge
on the serial clock has the second leading zero provided and also
clocks out address bit ADD1. The final bit in the data transfer is
valid on the 16th falling edge, having been clocked out on the
previous (15th) falling edge.
CS
SCLK
DOUT
DIN
t
2
t
3
t
9
SEQ1
t
4
t
7
t
5
t
11
t
8
t
QUIET
t
6
t
CONVERT
1
2
3
4
5
6
11
12
13
14
15
16
THREE-
STATE
ZERO
ADD1
2 IDENTIFICATION
BITS
ADD0
DB11
DB10
DB4
DB3
DB2
DB1
DB0
THREE-
STATE
t
10
ZERO
B
WRITE
DONTC
DONTC
ADD1
ADD0
CODING
DONTC
DONTC
DONTC
DONTC
Figure 16. Serial Interface Timing Diagram
CS
t
QUIET
MIN
t
CYCLE
5 s MIN
1
16
1
16
1
16
SCLK
VALID DATA
VALID DATA
DOUT
POWER-UP
DIN
Figure 17. General Timing Diagram
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