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參數(shù)資料
| 型號(hào)： | EVAL-AD7923CB2 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP |
| 中文描述： | 4通道，200 kSPS的，12位序列ADC的16引腳TSSOP |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 430K |
| 代理商： | EVAL-AD7923CB2 |
–10–
AD7923
REV. 0
Table III. Power Mode Selection
PM1 PM0 Mode
1
1
Normal Operation
. In this mode, the AD7923 remains in full power mode, regardless of the status of any of the logic
inputs. This mode allows the fastest possible throughput rate from the AD7923.
Full Shutdown
. In this mode, the AD7923 is in full shutdown mode with all circuitry on the AD7923 powering down.
The AD7923 retains the information in the Control Register while in full shutdown. The part remains in full shutdown
until these bits are changed.
Auto Shutdown
. In this mode, the AD7923 automatically enters full shutdown mode at the end of each conversion
when the Control Register is updated. Wake-up time from full shutdown is 1
m
s, and the user should ensure that 1
m
s has
elapsed before attempting to perform a valid conversion on the part in this mode.
Invalid Selection
. This configuration is not allowed.
1
0
0
1
0
0
SEQUENCER OPERATION
The configuration of the SEQ1 and SEQ0 bits in the Control
Register allows the user to select a particular mode of operation
of the sequencer function. Table IV outlines the three modes of
operation of the sequencer.
Table IV. Sequence Selection
SEQ1 SEQ0 Sequence Type
0
X
This configuration means that the sequence function is not used. The analog input channel selected for each
individual conversion is determined by the contents of the channel address bits ADD1, ADD0 in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer
function being used, where each write to the AD7923 selects the next channel for conversion. (See Figure 2.)
If the SEQ1 and SEQ0 bits are set in this way, the sequence function will not be interrupted upon completion of the
WRITE operation. This allows other bits in the Control Register to be altered between conversions while in a
sequence without terminating the cycle.
This configuration is used in conjunction with the channel address bits ADD1, ADD0 to program continuous
conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the
channel address bits in the Control Register. (See Figure 3.)
1
0
1
1
Table II. Channel Selection
ADD1
ADD0
Analog Input Channel
0
0
1
1
0
1
0
1
V
IN
0
V
IN
1
V
IN
2
V
IN
3
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