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參數(shù)資料
| 型號： | EVAL-AD7866CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface |
| 中文描述： | 雙1 MSPS的12位，雙通道SAR型ADC的串行接口 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 304K |
| 代理商： | EVAL-AD7866CB |
REV. 0
AD7866
–6–
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic
Function
11
RANGE
Analog Input Range and Output Coding Selection Pin. Logic Input. The polarity on this pin will
determine what input range the analog input channels on the AD7866 will have, and it will also
select what type of output coding the ADC will use for the conversion result. On the falling edge of
CS
, the polarity of this pin is checked to determine the analog input range of the next conversion. If
this pin is tied to a logic low, the analog input range is 0 V to V
REF
and the output coding from the
part will be straight binary (for the next conversion). If this pin is tied to a logic high when
CS
goes
low, the analog input range is 2
×
V
REF
and the output coding for the part will be two’s complement.
However, if after the falling edge of
CS
the logic level of the RANGE pin has changed upon the eighth
SCLK falling edge, the output coding will change to the other option without any change in the
analog input range. (See Analog Input and ADC Transfer Function sections.)
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on
the AD7866. The AV
DD
and DV
DD
voltages should ideally be at the same potential and must not
be more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND.
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7866. The DV
DD
and AV
DD
voltages should ideally be at the same potential and must not be
more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The
DGND and AGND voltages should ideally be at the same potential and must not be more than
0.3 V apart even on a transient basis.
Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously
from the simultaneous conversions of both ADCs. The data stream consists of one leading zero
followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided
MSB first. If
CS
is held low for a further 16 SCLK cycles after the conversion data has been output
on either D
OUT
A or D
OUT
B, the data from the other ADC follows on the D
OUT
pin. This allows
data from a simultaneous conversion on both ADCs to be gathered in serial format on either D
OUT
A
or D
OUT
B alone using only one serial port. See Serial Interface section.
Logic Power Supply Input. The voltage supplied at this pin determines what voltage the interface
will operate at. This pin should be decoupled to DGND.
Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the
AD7866. This clock is also used as the clock source for the conversion process.
Chip Select. Active low logic input. This input provides the dual function of initiating conversions
on the AD7866 and also frames the serial data transfer.
Multiplexer Select. Logic Input. This input is used to select the pair of channels to be converted
simultaneously, i.e. Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and
ADC B. The logic state of this pin is checked upon the falling edge of
CS
and the multiplexer is set
up for the
next
conversion. If it is low, the following conversion will be performed on Channel 1 of
each ADC; if it is high, the following conversion will be performed on Channel 2 of each ADC.
12
AV
DD
13
DV
DD
14
DGND
15, 16
D
OUT
A, D
OUT
B
17
V
DRIVE
18
SCLK
19
CS
20
A0
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