參數(shù)資料
型號： EVAL-AD7866CB
廠商： Analog Devices, Inc.
英文描述： Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
中文描述： 雙1 MSPS的12位，雙通道SAR型ADC的串行接口
文件頁數(shù)： 2/20頁
文件大?。?/td> 304K
代理商： EVAL-AD7866CB
REV. 0
–2–
AD7866–SPECIFICATIONS
1
(T
A
= T
MIN
to T
MAX
, V
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, Reference = 2.5 V
External on D
CAP
A and D
CAP
B, f
SCLK
= 20 MHz, unless otherwise noted.)
Parameter
A Version
1
B Version
1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise (SFDR)
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Channel to Channel Isolation
68
–75
–76
68
–75
–76
dB min
dB max
dB max
f
IN
= 300 kHz Sine Wave, f
S
= 1 MSPS
f
IN
= 300 kHz Sine Wave, f
S
= 1 MSPS
f
IN
= 300 kHz Sine Wave, f
S
= 1 MSPS
–88
–88
–88
–88
–88
–88
dB typ
dB typ
dB typ
SAMPLE AND HOLD
Aperture Delay
3
Aperture Jitter
3
Aperture Delay Matching
3
Full Power Bandwidth
10
50
200
12
2
10
50
200
12
2
ns max
ps typ
ps max
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
Integral Nonlinearity
12
±
1.5
12
±
1
±
1.5
–0.95/+1.25
Bits
LSB max
LSB max
LSB max
B Grade, 0 V to V
REF
range only;
±
0.5 LSB typ
0 V to 2
×
V
REF
range;
±
0.5
LSB
typ
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding
Differential Nonlinearity
0 V to V
REF
Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
2
×
V
REF
Input Range
Positive Gain Error
Zero Code Error
Zero Code Error Match
Negative Gain Error
–0.95/+1.25
±
8
±
1.2
±
2.5
±
0.2
±
8
±
1.2
±
2.5
±
0.2
LSB max
LSB typ
LSB max
LSB typ
–V
REF
to +V
REF
Biased about V
REF
with
Two’s Complement Output Coding
±
2.5
±
8
±
0.2
±
2.5
±
2.5
±
8
±
0.2
±
2.5
LSB max
LSB max
LSB typ
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to V
REF
0 to 2
V
REF
0 to 2
V
REF
±
500
30
10
0 to V
REF
V
V
nA max
pF typ
pF typ
RANGE Pin Low upon
CS
Falling Edge
RANGE Pin High upon
CS
Falling Edge
DC Leakage Current
Input Capacitance
±
500
30
10
When in Track
When in Hold
REFERENCE INPUT/OUTPUT
Reference Input Voltage
Reference Input Voltage Range
4
DC Leakage Current
2.5
2/3
±
30
±
160
20
2.45/2.55
25
45
50
±
15
2.5
2/3
±
30
±
160
20
2.45/2.55
25
45
50
±
15
V
V min/V max REF SELECT Pin Tied High
μ
A max
V
REF
Pin;
μ
A max
D
CAP
A, D
CAP
B Pins;
pF typ
V min/V max
typ
V
DD
= 5 V
typ
V
DD
= 3 V
ppm/
°
C typ
mV typ
±
1% for Specified Performance
Input Capacitance
Reference Output Voltage
5
V
REF
Output Impedance
6
Reference Temperature Coefficient
REF OUT Error (T
MIN
to T
MAX
)
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
0.7 V
DRIVE
0.3 V
DRIVE
±
1
10
0.7 V
DRIVE
0.3 V
DRIVE
±
1
10
V min
V max
μ
A max
pF max
Typically 15 nA, V
IN
= 0 V or V
DRIVE
V
DRIVE
– 0.2
0.4
±
1
10
Straight (Natural) Binary
Two’s Complement
V
DRIVE
– 0.2
0.4
±
1
10
V min
V max
μ
A max
pF max
I
SOURCE
= 200
μ
A
I
SINK
= 200
μ
A
V
DD
= 2.7 V to 5.25 V
Selectable with Either Input Range
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