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參數(shù)資料
| 型號： | EVAL-AD7731EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7731 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.4k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±1.28 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 67.5mW @ 6.4kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7731 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7731BNZ-ND - IC ADC 24BIT SIGMA-DELTA 24DIP AD7731BRUZ-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRUZ-REEL-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRUZ-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRZ-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRZ-REEL-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRZ-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRU-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRU-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BR-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC 更多... |
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AD7731
–17–
REV. 0
Bit
Location
Mnemonic
Description
MR12
B/U
Bipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is
00...000 for negative full-scale input, 10...000 for zero input and 11...111 for positive full-
scale input. A 1 in this bit selects unipolar operation and the output coding is 00...000 for
zero input and 11...111 for positive full-scale input.
MR11
DEN
Digital Output Enable Bit. With this bit at 1, the AIN3/D1 and AIN4/D0 pins assume their
digital output functions and the output drivers connected to these pins are enabled. In this
mode, the user effectively has two port bits which can be programmed over the serial interface.
MR10–MR9
D1–D0
Digital Output Bits. These bits determine the digital outputs on the AIN3/D1 and AIN4/D0
pins respectively when the DEN bit is a 1. For example, a 1 written to the D1 bit of the
Mode Register (with the DEN bit also a 1) will put a logic 1 on the AIN3/D1 pin. This logic
1 will remain on this pin until a 0 is written to the D1 bit (in which case, the AIN3/D1 pin
goes to a logic 0) or the digital output function is disabled by writing a 0 to the DEN bit.
MR8
WL
Data Word Length Bit. This bit determines the word length of the Data Register. A 0 in this
bit selects 16-bit word length when reading from the data register (i.e.,
RDY returns high
after 16 serial clock cycles in the read operation). A 1 in this bit selects 24-bit word length for
the Data Register.
MR7
HIREF
High Reference Bit. This bit should be set in accordance with the reference voltage which is
being used on the part. If the reference voltage is 2.5 V, the HIREF bit should be set to 0. If
the reference voltage is 5 V, the HIREF bit should be set to a 1. With the HIREF bit set
correctly for the appropriate applied reference voltage, the input ranges are 0 mV to +20 mV,
+40 mV, +80 mV, +160 mV, +320 mV, +640 mV and +1.28 V for unipolar operation and
±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV and ±1.28 V for bipolar operation.
It is possible for a user with a 2.5 V reference to set the HIREF bit to a 1. In this case, the
part is operating with a 2.5 V reference but assumes it has a 5 V reference. As a result, the
input ranges on the part become 0 mV to +10 mV through 0 mV to +640 mV for unipolar
operation and
±10 mV through ±640 mV for bipolar operation. However, the output noise
from the part (in nV) will remain unchanged so the resolution of the part (in LSBs) will re-
duce by 1.
MR6–MR4
RN2–RN0
Input Range Bits. These bits determine the analog input range for the selected analog input.
The different input ranges are outlined in Table XII. The table is valid for a reference voltage
of 2.5 V with the HIREF bit at 0 or for a reference voltage of 5 V with the HIREF bit at a
logic 1.
Table XII. Input Range Selection
Input Range
RN2
RN1
RN0
B/U Bit = 0
B/U Bit = 1
0
–20 mV to +20 mV
0 mV to +20 mV
0
1
–20 mV to +20 mV
0 mV to +20 mV
0
1
0
–40 mV to +40 mV
0 mV to +40 mV
0
1
–80 mV to +80 mV
0 mV to +80 mV
1
0
–160 mV to +160 mV
0 mV to +160 mV
1
0
1
–320 mV to +320 mV
0 mV to +320 mV
1
0
–640 mV to +640 mV
0 mV to +640 mV
1
–1.28 V to +1.28 V
0 mV to +1.28 V
Power-On/Reset Default
REV. A
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