參數(shù)資料
型號(hào)： EVAL-AD5932EB
廠商： Analog Devices, Inc.
英文描述： Programmable Frequency Scan Waveform Generator
中文描述： 可編程頻率掃描信號(hào)發(fā)生器
文件頁(yè)數(shù)： 21/28頁(yè)
文件大?。?/td> 410K
代理商： EVAL-AD5932EB
AD5932
AD5932 TO 68HC11/68L11 INTERFACE
Figure 35 shows the serial interface between the AD5932 and
the 68HC11/68L11 microcontroller. The microcontroller is
configured as the master by setting Bit MSTR in the SPCR to 1,
which provides a serial clock on SCK while the MOSI output
drives the serial data line, SDATA. Because the microcontroller
does not have a dedicated frame sync pin, the FSYNC signal is
derived from a port line (PC7). The set-up conditions for
correct operation of the interface are as follows:
Rev. 0 | Page 21 of 28
To load the remaining eight bits to the AD5932, P3.3 is held low
after the first eight bits have been transmitted, and a second
write operation is initiated to transmit the second byte of data.
P3.3 is taken high following completion of the second write
operation. SCLK should idle high between the two write
operations. The 80C51/80L51 outputs the serial data in an LSB-
first format. The AD5932 accepts the MSB first (the four MSBs
being the control information, the next four bits being the
address, while the eight LSBs contain the data when writing to a
destination register). Therefore, the transmit routine of the
80C51/80L51 must consider this and rearrange the bits so that
the MSB is output first.
SCK idles high between write operations (CPOL = 0).
Data is valid on the SCK falling edge (CPHA = 1).
AD5932
1
80C51/80L51
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 36. 80C51/80L51 to AD5932 Interface
P3.3
RxD
TxD
FSYNC
0
SDATA
SCLK
When data is being transmitted to the AD5932, the FSYNC line
is taken low (PC7). Serial data from the 68HC11/68L11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data into the AD5932, PC7 is held low after the
first eight bits are transferred and a second serial write operation is
performed to the AD5932. Only after the second eight bits have
been transferred should FSYNC be taken high again.
AD5932
1
68HC11/68L11
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. 68HC11/68L11 to AD5932 Interface
PC7
MOSI
SCK
FSYNC
0
SDATA
SCLK
AD5932 TO DSP56002 INTERFACE
Figure 37 shows the interface between the AD5932 and the
DSP56002. The DSP56002 is configured for normal mode,
asynchronous operation with a gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated internally
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0),
and the frame sync signal frames the 16 bits (FSL = 0). The
frame sync signal is available on Pin SC2, but it must be
inverted before being applied to the AD5932. The interface to
the DSP56000/DSP56001 is similar to that of the DSP56002.
AD5932 TO 80C51/80L51 INTERFACE
Figure 36 shows the serial interface between the AD5932 and
the 80C51/80L51 microcontroller. The microcontroller is
operated in Mode 0 so that TxD of the 80C51/80L51 drives
SCLK of the AD5932, while RxD drives the serial data line
SDATA. The FSYNC signal is again derived from a bit program-
mable pin on the port (P3.3 being used in the diagram). When
data is to be transmitted to the AD5932, P3.3 is taken low. The
80C51/80L51 transmits data in 8-bit bytes; thus, only eight
falling SCLK edges occur in each cycle.
AD5932
1
DSP56002
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. DSP56002 to AD5932 Interface
SC2
STD
SCK
FSYNC
0
SDATA
SCLK
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