- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362800 > EVAL-AD5932EB (Analog Devices, Inc.) Programmable Frequency Scan Waveform Generator PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-AD5932EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Programmable Frequency Scan Waveform Generator |
| 中文描述： | 可編程頻率掃描信號(hào)發(fā)生器 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 410K |
| 代理商： | EVAL-AD5932EB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD5932
PROGRAMMING THE AD5932
The AD5932 is designed to provide automatic frequency scans
when the CTRL pin is triggered. The scan is controlled by a set
of registers, the addresses of which are given in Table 5. The
function of each register is described in more detail in the
Setting Up the Frequency Scan section.
Rev. 0 | Page 16 of 28
The Control Register
The AD5932 contains a 12-bit control register that sets up the
operating modes, as shown in the following bit map.
D15
0
D14
0
D13
0
D12
0
D11 to D0
Control bits
This register controls the different functions and the various
output options from the AD5932. Table 6 describes the
individual bits of the control register.
To address the control register, D15 to D12 of the 16-bit serial
word must be set to 0.
Table 6. Description of Bits in the Control Register
Bit
Name
Function
D15 to D12
ADDR
Register address bits.
D11
B24
Two write operations are required to load a complete word into the F
START
register and the Δf register.
When B24 = 1, a complete word is loaded into a frequency register in two consecutive writes. The first
write contains the 12 LSBs of the frequency word and the next write contains the 12 MSBs. Refer to Table 5
for the appropriate addresses. The write to the destination register occurs after both words have been loaded,
so the register never holds an intermediate value.
When B24 = 0, the 24-bit F
START
/Δf register operates as two 12-bit registers, one containing the 12 MSBs
and the other containing the 12 LSBs. This means that the 12 MSBs of the frequency word can be altered
independently of the 12 LSBs and vice versa. This is useful if the complete 24-bit update is not required.
To alter the 12 MSBs or the 12 LSBs, a single write is made to the appropriate register address. Refer to Table 5
for the appropriate addresses.
D10
DAC ENABLE
When DAC ENABLE = 1, the DAC is enabled.
When DAC ENABLE = 0, the DAC is powered down. This saves power and is beneficial when using only
the MSB of the DAC input data (available at the MSBOUT pin).
D9
SINE/TRI
The function of this bit is to control what is available at the VOUT pin.
When SINE/TRI = 1, the SIN ROM is used to convert the phase information into amplitude information,
resulting in a sinusoidal signal at the output.
When SINE/TRI = 0, the SIN ROM is bypassed, resulting in a triangular (up-down) output from the DAC.
D8
MSBOUTEN
When MSBOUTEN = 1, the MSBOUT pin is enabled.
When MSBOUTEN = 0, the MSBOUT is disabled (three-state).
D7
Reserved
This bit must be set to 1.
D6
Reserved
This bit must be set to 1.
D5
INT/EXT INCR
When INT/EXT INCR = 1, the frequency increments are triggered externally through the CTRL pin.
When INT/EXT INCR = 0, the frequency increments are triggered automatically.
D4
Reserved
This bit must be set to 1.
D3
SYNCSEL
This bit is active when D2 = 1. It is user-selectable to pulse at end of scan (EOS) or at each frequency
increment. When SYNCSEL = 1, the SYNCOUT pin outputs a high level at end of scan and returns to 0
at the start of the subsequent scan.
When SYNCSEL= 0, the SYNCOUT outputs a pulse of 4 × T
CLOCK
only at each frequency increment.
D2
SYNCOUTEN
When SYNCOUTEN = 1, the SYNC output is available at the SYNCOUT pin.
When SYNCOUTEN = 0, the SYNCOP pin is disabled (three-state).
D1
Reserved
This bit must be set to 1.
D0
Reserved
This bit must be set to 1.
Table 5. Register Addresses
Register Address
D15
D14
D13
0
0
0
0
0
0
0
0
1
Mnemonic
C
REG
N
INCR
Δ
f
Name
Control bits
Number of increments
Lower 12 bits of
delta frequency
Higher 12 bits of
delta frequency
Increment interval
Reserved
Lower 12 bits of
start frequency
Higher 12 bits of
start frequency
Reserved
Reserved
D12
0
1
0
0
0
1
1
Δ
f
0
1
1
1
0
1
0
0
t
INT
F
START
1
1
0
1
F
START
1
1
1
1
1
1
0
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-AD5934EB | 250 kSPS, 12-Bit Impedance Converter, Network Analyzer |
| EVAL-AD7143-1EBZ | Programmable Controller for Capacitance Touch Sensors |
| EVAL-AD7147-1EBZ | CapTouch⑩ Programmable Controller for Single-Electrode Capacitance Sensors |
| EVAL-AD7147EBZ | CapTouch⑩ Programmable Controller for Single-Electrode Capacitance Sensors |
| EVAL-AD7265CB1 | Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD5932EBZ | 功能描述:BOARD EVAL FOR AD5932 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVALAD5933EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Evaluation Board for the 1 MSPS 12-Bit Impedance Converter Network Analyzer |
| EVAL-AD5933EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD5933EB-U1 | 制造商:Analog Devices 功能描述:- Bulk |
| EVAL-AD5933EBZ | 功能描述:BOARD EVALUATION FOR AD5933 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。