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參數(shù)資料
| 型號： | EVAL-AD5932EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Programmable Frequency Scan Waveform Generator |
| 中文描述： | 可編程頻率掃描信號發(fā)生器 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 410K |
| 代理商： | EVAL-AD5932EB |
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AD5932
APPLICATIONS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD5932 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes because it
gives the best shielding. Digital and analog ground planes
should be joined in only one place. If the AD5932 is the only
device requiring an AGND-to-DGND connection, then the
ground planes should be connected at the AGND and DGND
pins of the AD5932. If the AD5932 is in a system where
multiple devices require AGND-to-DGND connections, the
connection should be made at one point only, a star ground
point that should be established as close as possible to the
AD5932.
Rev. 0 | Page 20 of 28
Interfacing to Microprocessors
The AD5932 has a standard serial interface that allows the part
to interface directly with several microprocessors. The device
uses an external serial clock to write the data/control informa-
tion into the device. The serial clock can have a frequency of
40 MHz maximum. The serial clock can be continuous, or it
can idle high or low between write operations. When data/control
information is being written to the AD5932, FSYNC is taken
low and is held low while the 16 bits of data are being written
into the AD5932. The FSYNC signal frames the 16 bits of
information being loaded into the AD5932.
AD5932 TO ADSP-21XX INTERFACE
Figure 34 shows the serial interface between the AD5932 and
the ADSP-21xx. The ADSP-21xx should be set up to operate in
the SPORT transmit alternate framing mode (TFSW = 1). The
ADSP-21xx are programmed through the SPORT control
register and should be configured as follows:
Avoid running digital lines under the device because these
couple noise onto the die. The analog ground plane should run
under the AD5932 to avoid noise coupling. The power supply
lines to the AD5932 should use as large a track as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals, such as clocks,
should be shielded with digital ground to avoid radiating noise
to other sections of the board. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board should run
at right angles to each other, reducing the effects of feedthrough.
A microstrip technique is by far the best but is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground planes,
while signals are placed on the other side.
Internal clock operation (ISCLK = 1)
Active low framing (INVTFS = 1)
16-bit word length (SLEN = 15)
Internal frame sync signal (ITFS = 1)
Generation of a frame sync for each write (TFSR = 1)
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. The data is clocked out on
each rising edge of the serial clock and clocked into the AD5932
on the SCLK falling edge.
Good decoupling is important. The analog and digital supplies
to the AD5932 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND, respectively, with 0.1 μF ceramic capacitors
in parallel with 10 μF tantalum capacitors. To achieve the best
from the decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the AVDD
and DVDD of the AD5932, it is recommended that the system’s
AVDD supply be used. This supply should have the recom-
mended analog supply decoupling between the AVDD pin of
the AD5932 and AGND and the recommended digital supply
decoupling capacitors between the DVDD pin and DGND.
AD5932
1
ADSP-2101/
ADSP-2103
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
TFS
DT
SCLK
FSYNC
0
SDATA
SCLK
Figure 34. ADSP-2101/ADSP-2103 to AD5932 Interface
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| EVAL-AD5932EBZ | 功能描述:BOARD EVAL FOR AD5932 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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| EVAL-AD5933EBZ | 功能描述:BOARD EVALUATION FOR AD5933 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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