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| 型號： | EVAL-AD1937AZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1937 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻編解碼器 |
| 已用 IC / 零件： | AD1937 |
| 主要屬性： | 24 位，192 kHz，4 ADC: 107dB 動(dòng)態(tài)范圍，8 DAC: 112dB 動(dòng)態(tài)范圍 |
| 次要屬性： | 分時(shí)復(fù)用（TDM）、I2C 和 SPI 接口，Popguard? 技術(shù) |
| 已供物品： | 板 |
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AD1937
Rev. B | Page 16 of 36
To maintain the highest performance possible, limit the clock jitter
of the internal master clock signal to less than a 300 ps rms time
interval error (TIE). Even at these levels, extra noise or tones
can appear in the DAC outputs if the jitter spectrum contains
large spectral peaks. If the internal PLL is not used, it is best to
use an independent crystal oscillator to generate the master clock.
In addition, it is especially important that the clock signal not
pass through an FPGA, CPLD, or other large digital chip (such
as a DSP) before being applied to the AD1937. In most cases,
this induces clock jitter due to the sharing of common power
and ground connections with other unrelated digital output
signals. When the PLL is used, jitter in the reference clock is
attenuated above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
The function of the PD/RST pin sets all the control registers to
their default settings. To avoid audio pops, PD/RST does not
power down the analog outputs. After PD/RST is deasserted
and the PLL acquires lock condition, an initialization routine
runs inside the AD1937. This initialization lasts for approx-
imately 256 master clock cycles. Once the routine is complete,
the registers can be programmed.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down their
respective sections. All other register settings are retained.
To guarantee proper startup, the PD/RST pin should be
pulled low by an external resistor.
I2C CONTROL PORT
The AD1937 has an I2C-compatible control port that permits
programming and reading back the internal control registers
for the ADCs, DACs, and clock system. There is also a stand-
alone mode available for operation without serial control,
configured at reset using the serial control pins. All registers
are set to default except internal MCLK enable, which is set to
1 and ADC BCLK and LRCLK master/slave is set by SDA (see
Table 12 for details).
Table 12. Hardware Selection of Standalone Mode
ADC Clocks
ADDR0
(Pin 30)
SDA
(Pin 31)
SCL
(Pin 34)
ADDR1
(Pin 35)
Slave
0
Master
0
1
0
The I2C interface of the AD1937 is a 2-wire interface that
consists of a clock line (SCL) and a data line (SDA). SDA
is bidirectional and the AD1937 drives SDA either to acknowl-
edge the master (ACK) or to send data during a read operation.
The SDA pin for the I2C port is an open-drain collector and
requires a 2 kΩ pull-up resistor. A write or read access occurs
when the SDA line is pulled low while the SCL line is high,
indicated by start in the timing diagrams. SDA is only allowed
to change when SCL is low except when a start or stop condition
of the data-word consist of the device address and the R/W bit.
The device address consists of an internal built-in address
(0x08) OR’ed with the two address bits, ADDR1 and ADDR0,
and the R/W bit. The two address bits allow four AD1937s to be
used in a system. Tie I2C ADDR0 and ADDR1 low or high and
program the ADDR bits accordingly as 0 or 1. Initiating a write
operation to the AD1937 involves sending a start condition and
then sending the device address with the R/W bit set low. The
AD1937 responds by issuing an acknowledge to indicate that it
has been addressed. The user then sends a second frame telling
the AD1937 which register is required to be written to. Another
acknowledge is issued by the AD1937. Finally, the user can send
another frame with the eight data bits required to be written to
the register. A third acknowledge is issued by the AD1937 after
which the user can send a stop condition to complete the data
transfer.
A read operation requires that the user first write to the
AD1937 to point to the correct register and then read the
data. This is achieved by sending a start condition followed
by the device address frame, with the R/W bit low; the AD1937
returns an acknowledge. The master then sends the register
address frame. Following the acknowledge from the AD1937,
the user must issue a repeated start condition. The next frame
is the device address with the R/W bit set high; the AD1937
returns an acknowledge. On the next frame, the AD1937
outputs the register data on the SDA line; the master should
send an acknowledge. A stop condition completes the read
operation.
and
show examples of writing
to and reading from the DAC1L volume control register,
Address 0x06 (see
).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1937EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| EVAL-AD1937EBZ | 制造商:Analog Devices 功能描述:EB SINGLE CHIP CODEC 4 ADC'S W/DIFF OUTP - Boxed Product (Development Kits) |
| EVAL-AD1938AZ | 功能描述:BOARD EVAL FOR AD1938 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-AD1938EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24-Bit CODEC |
| EVAL-AD1938EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR MULTI CHANNEL 96KHZ CODEC - Boxed Product (Development Kits) |
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