參數(shù)資料
型號(hào): EVAL-AD1937AZ
廠商: Analog Devices Inc
文件頁數(shù): 3/36頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD1937
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻編解碼器
已用 IC / 零件: AD1937
主要屬性: 24 位,192 kHz,4 ADC: 107dB 動(dòng)態(tài)范圍,8 DAC: 112dB 動(dòng)態(tài)范圍
次要屬性: 分時(shí)復(fù)用(TDM)、I2C 和 SPI 接口,Popguard? 技術(shù)
已供物品:
AD1937
Rev. B | Page 11 of 36
NC = NO CONNECT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
64
NC
63
AV
DD
62
LF
61
ADC2RN
60
ADC2RP
59
ADC2L
N
58
ADC2L
P
57
ADC1RN
56
ADC1RP
55
ADC1L
N
54
ADC1L
P
53
CM
52
AV
DD
51
NC
50
NC
49
DV
DD
17
DS
D
AT
A
3
18
DS
D
AT
A
2
19
DS
D
AT
A
1
20
DBCL
K
21
DL
R
CL
K
22
VS
U
PP
L
Y
23
VS
EN
S
E
24
VD
R
IVE
25
AS
D
AT
A
2
26
AS
D
AT
A
1
27
ABCL
K
28
AL
R
CL
K
29
AD
DR0
30
SD
A
31
AGND
1
DV
DD
32
MCLKI/MCLKXI 2
MCLKO/MCLKXO 3
AGND
4
AVDD
5
DAC3LP
6
DAC3LN
7
DAC3RP
8
DAC3RN
9
DAC4LP 10
DAC4LN 11
DAC4RP 12
DAC4RN 13
PD/RST 14
AGND
48
FILTR
47
AGND
46
AVDD
45
AGND
44
DAC2RN
43
DAC2RP
42
DAC2LN
41
DAC2LP
40
DAC1RN
39
DAC1RP
38
DAC1LP
36
ADDR1
35
DSDATA4 15
SCL
34
DGND 16
DGND
33
DAC1LN
37
AD1937
TOP VIEW
(Not to Scale)
DIFFERENTIAL OUTPUT
07
41
4-
00
2
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
Type 1
Mnemonic
Description
1, 4, 44, 46, 48
I
AGND
Analog Ground.
2
I
MCLKI/MCLKXI
Master Clock Input/Crystal Oscillator Input.
3
O
MCLKO/MCLKXO
Master Clock Output/Crystal Oscillator Output.
5, 45, 51, 62
I
AVDD
Analog Power Supply. Connect this pin to analog 3.3 V supply.
6
O
DAC3LP
DAC3 Left Positive Output.
7
O
DAC3LN
DAC3 Left Negative Output.
8
O
DAC3RP
DAC3 Right Positive Output.
9
O
DAC3RN
DAC3 Right Negative Output.
10
O
DAC4LP
DAC4 Left Positive Output.
11
O
DAC4LN
DAC4 Left Negative Output.
12
O
DAC4RP
DAC4 Right Positive Output.
13
O
DAC4RN
DAC4 Right Negative Output
14
I
PD/RST
Power-Down Reset (Active Low).
15
I/O
DSDATA4
DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line mode)/
AUX DAC2 data out (to external DAC2).
16, 33
I
DGND
Digital Ground.
17, 32
I
DVDD
Digital Power Supply. Connect this pin to digital 3.3 V supply.
18
I/O
DSDATA3
DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line mode)/AUX
ADC2 data in (from external ADC2).
19
I/O
DSDATA2
DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1 data in
(from external ADC1).
20
I
DSDATA1
DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.
21
I/O
DBCLK
Bit Clock for DACs. Can be programmed as input or output in all modes.
22
I/O
DLRCLK
Frame Clock for DACs. Can be programmed as input or output in all modes.
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