參數(shù)資料
型號(hào): EPM9320A
廠商: Altera Corporation
英文描述: Programmable Logic Device Family(MAX9000可編程邏輯系列器件)
中文描述: 可編程邏輯器件系列(MAX9000可編程邏輯系列器件)
文件頁(yè)數(shù): 27/41頁(yè)
文件大?。?/td> 604K
代理商: EPM9320A
Altera Corporation
27
MAX 9000 Programmable Logic Device Family Data Sheet
Timing Model
The continuous, high-performance FastTrack Interconnect ensures
predictable performance and accurate simulation and timing analysis.
This predictable performance contrasts with that of FPGAs, which use a
segmented connection scheme and hence have unpredictable
performance. Timing simulation and delay prediction are available with
the MAX+PLUS II Simulator and Timing Analyzer, or with industry-
standard EDA tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with 0.1-ns resolution. The Timing Analyzer provides point-
to-point timing delay information, setup and hold time prediction, and
device-wide performance analysis.
The MAX 9000 timing model in
Figure 14
shows the delays that
correspond to various paths and functions in the circuit. This model
contains three distinct parts: the macrocell, IOC, and interconnect,
including the row and column FastTrack Interconnect and LAB local
array paths. Each parameter shown in
Figure 14
is expressed as a worst-
case value in the internal timing characteristics tables in this data sheet.
Hand-calculations that use the MAX 9000 timing model and these timing
parameters can be used to estimate MAX 9000 device performance.
f
For more information on calculating MAX 9000 timing delays, see
Application Note 77 (Understanding MAX 9000 Timing)
in this data book.
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