參數(shù)資料
型號: EPM7128B
廠商: Altera Corporation
英文描述: Programmable Logic Device Family(MAX7000B可編程邏輯系列器件)
中文描述: 可編程邏輯器件系列(MAX7000B可編程邏輯系列器件)
文件頁數(shù): 39/125頁
文件大?。?/td> 1053K
代理商: EPM7128B
Altera Corporation
39
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
Tables 25
and
26
show EPM7128B AC operating conditions.
Table 25. EPM7128B External Timing Parameters
Notes (1)
,
(2)
Symbol
Parameter
Conditions
Speed Grade
Unit
-4
-7
-10
Min
Max
Min
Max
Min
Max
t
PD1
Input to non-registered
output
C1 = 35 pF
(3)
4.5
7.5
10.0
ns
t
PD2
I/O input to non-registered
output
C1 = 35 pF
(3)
4.5
7.5
10.0
ns
t
SU
t
H
t
FSU
Global clock setup time
(3)
3.5
0.0
1.0
5.6
0.0
1.5
7.5
0.0
1.5
ns
ns
ns
Global clock hold time
(3)
Global clock setup time of
fast input
t
FH
Global clock hold time of
fast input
1.0
1.0
1.0
ns
t
FZHSU
Global clock setup time of
fast input with zero hold
time
2.5
3.0
3.0
ns
t
FZHH
Global clock hold time of
fast input with zero hold
time
0.0
0.0
0.0
ns
t
CO1
Global clock to output
delay
C1 = 35 pF
1.0
2.5
1.0
4.3
1.0
5.6
ns
t
CH
t
CL
t
ASU
t
AH
t
ACO1
t
ACH
t
ACL
t
CPPW
Global clock high time
2.0
2.0
2.1
0.0
1.0
2.0
2.0
2.0
3.0
3.0
3.5
0.0
1.0
3.0
3.0
3.0
4.0
4.0
4.6
0.0
1.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
Global clock low time
Array clock setup time
(3)
Array clock hold time
(3)
Array clock to output delay
C1 = 35 pF
(3)
3.9
6.4
8.5
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
t
CNT
Minimum global clock
period
(3)
4.7
7.8
10.2
ns
f
CNT
Maximum internal global
clock frequency
(3)
,
(4)
212.8
128.2
98.0
MHz
t
ACNT
Minimum array clock
period
(3)
4.7
7.8
10.2
ns
f
ACNT
Maximum internal array
clock frequency
(3)
,
(4)
212.8
128.2
98.0
MHz
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