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參數(shù)資料
| 型號： | EPF8452AQC160-4 |
| 廠商： | Altera |
| 文件頁數(shù)： | 2/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 8000A FPGA 4K 160-PQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 系列： | FLEX 8000 |
| LAB/CLB數(shù)： | 42 |
| 邏輯元件/單元數(shù)： | 336 |
| 輸入/輸出數(shù)： | 120 |
| 門數(shù)： | 4000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 產(chǎn)品目錄頁面： | 602 (CN2011-ZH PDF) |
| 其它名稱： | 544-2259 |
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10
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
The MAX+PLUS II Compiler can create cascade chains automatically
during design processing; designers can also insert cascade chain logic
manually during design entry. Cascade chains longer than eight LEs are
automatically implemented by linking LABs together. The last LE of an
LAB cascades to the first LE of the next LAB.
Figure 5 shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. For a device with an A-2 speed grade,
the LE delay is 2.4 ns; the cascade chain delay is 0.6 ns. With the cascade
chain, 4.2 ns is needed to decode a 16-bit address.
Figure 5. FLEX 8000 Cascade Chain Operation
LE Operating Modes
The FLEX 8000 LE can operate in one of four modes, each of which uses
LE resources differently. See Figure 6. In each mode, seven of the ten
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. The three remaining
inputs to the LE provide clock, clear, and preset control for the register.
The MAX+PLUS II software automatically chooses the appropriate mode
for each application. Design performance can also be enhanced by
designing for the operating mode that supports the desired application.
d[3..0]
LE1
LUT
d[7..4]
LE2
LUT
d[(4
n-1)..4(n-1)]
LE
n
LUT
d[3..0]
LUT
d[7..4]
LUT
d[(4
n-1)..4(n-1)]
LUT
LE1
LE2
LE
n
AND Cascade Chain
OR Cascade Chain
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF8452AQC160-4N | 制造商:Altera Corporation 功能描述:FPGA FLEX 8000 Family 4K Gates 336 Cells 125MHz CMOS Technology 5V 160-Pin PQFP |
| EPF8452AQC160-5 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 336 Cell, 160 Pin, Plastic, QFP |
| EPF8452AQC160-6 | 制造商:Altera Corporation 功能描述: |
| EPF8452AQI160-3 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 336 Cell, 160 Pin, Plastic, QFP |
| EPF8452ATC100-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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