參數(shù)資料
型號(hào)： EPF10K100B
英文描述： Programmable Logic
中文描述： 可編程邏輯
文件頁數(shù)： 52/138頁
文件大?。?/td> 2116K
代理商： EPF10K100B
20
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a 4-input LUT. The MAX+PLUS II Compiler automatically
selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The
LUT output can be combined with the cascade-in signal to form a cascade
chain through the cascade-out signal. Either the register or the LUT can be
used to drive both the local interconnect and the FastTrack Interconnect at
the same time.
The LUT and the register in the LE can be used independently; this feature
is known as register packing. To support register packing, the LE has two
outputs; one drives the local interconnect and the other drives the
FastTrack Interconnect. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a 3-input function can be computed in the LUT, and a
fourth independent signal can be registered. Alternatively, a 4-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect while the LUT drives the local
interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a 3-input function, and the other generates a carry output. As
shown in Figure 9 on page 19, the first LUT uses the carry-in signal and
two data inputs from the LAB local interconnect to generate a
combinatorial or registered output. For example, in an adder, this output
is the sum of three signals: a, b, and carry-in. The second LUT uses the
same three signals to generate a carry-out signal, thereby creating a carry
chain. The arithmetic mode also supports simultaneous use of the cascade
chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
Two 3-input LUTs are used: one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
register control signals, without using the LUT resources.
相關(guān)PDF資料
PDF描述
EPF10K200S Programmable Logic
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EPF10K130EFC672-1 Field Programmable Gate Array (FPGA)
EPF10K130EFC672-1X Field Programmable Gate Array (FPGA)
EPF10K130EFC672-2 Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K100BFC256-1 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPF10K100BFC256-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100BFC256-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPF10K100BFC256-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100BFC256-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
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