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| 型號(hào)： | EPF10K100B |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁(yè)數(shù)： | 42/138頁(yè) |
| 文件大?。?/td> | 2116K |
| 代理商： | EPF10K100B |
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136
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
All pins that are not listed are user I/O pins.
(2)
This pin is a dedicated pin; it is not available as a user I/O pin.
(3)
This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function.
(4)
This pin can be used as a user I/O pin after configuration.
(5)
This pin is tri-stated in user mode.
(6)
The optional JTAG pin TRST is not used in the 100-pin or 144-pin TQFP package.
(7)
To maintain pin compatibility when transferring to the EPF10K10 or EPF10K10A device from any other device in
the 208-pin PQFP or 256-pin FineLine BGA package, do not use these pins as user I/O pins.
(8)
The user I/O pin count includes dedicated input pins, dedicated clock pins, and all I/O pins.
(9)
To maintain pin compatibility when transferring to the EPF10K30 device from any other device in the 356-pin BGA
or 484-pin FineLine BGA package, do not use these pins as user I/O pins.
(10) To maintain pin compatibility when transferring to the EPF10K50V device from any other device in the 484-pin
FineLine BGA package, do not use these pins as user I/O pins.
(11) To maintain pin compatibility when transferring from the EPF10K100 to the EPF10K70 in the 503-pin PGA package,
do not use these pins as user I/O pins.
(12) This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry
are locked to the incoming clock and generate an internal clock, LOCK is driven high. LOCK remains high if a periodic
clock stops clocking. The LOCK function is optional; if the LOCK output is not used, this pin is a user I/O pin.
(13) This pin drives the ClockLock and ClockBoost circuitry.
(14) This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power
and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the
rest of the device.
(15) To maintain pin compatibility when transferring to the EPF10K100A device from another device in the 600-pin BGA
package, do not use these pins as user I/O pins.
No Connect (N.C.)
–
D1, D2, D3, E1, E3,
E4, E32, F1, F2, F3,
F4, G1, G2, G3, G4,
G5, H5, D33, D34,
D35, E33, E34, E35,
F32, F33, F34, G31,
G32, G33, G34, G35,
H31, AB31, AB32,
AB33, AB34, AC31,
AC32, AC33, AC34,
AC35, AD31, AD32,
AD33, AD34, AE33,
AE34, AE35, AH5,
AJ2, AJ3, AJ4, AJ5,
AK1, AK2, AK3, AK4,
AK5, AL1, AL2, AL4,
AM1, AM2, AM3
–
Total User I/O Pins
406
470
406
470
Table 122. FLEX 10K Pin-Outs (Part 3 of 3)
Note (1)
Pin Name
503-Pin PGA
EPF10K100
599-Pin PGA
EPF10K130V
EPF10K250A
600-Pin BGA
EPF10K100A
600-Pin BGA
EPF10K130V
EPF10K250A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EPF10K200S | Programmable Logic |
| EPF10K130EFC484-3 | Field Programmable Gate Array (FPGA) |
| EPF10K130EFC672-1 | Field Programmable Gate Array (FPGA) |
| EPF10K130EFC672-1X | Field Programmable Gate Array (FPGA) |
| EPF10K130EFC672-2 | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K100BFC256-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K100BFC256-1DX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ASIC |
| EPF10K100BFC256-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K100BFC256-2DX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ASIC |
| EPF10K100BFC256-3DX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ASIC |
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