參數(shù)資料
型號: EPF10K100B
英文描述: Programmable Logic
中文描述: 可編程邏輯
文件頁數(shù): 49/138頁
文件大?。?/td> 2116K
代理商: EPF10K100B
18
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
LE Operating Modes
The FLEX 10K LE can operate in the following four modes:
s
Normal mode
s
Arithmetic mode
s
Up/down counter mode
s
Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. Quartus and
MAX+PLUS II software packages, in conjunction with parameterized
functions such as LPM and DesignWare functions, automatically chooses
the appropriate mode for common functions such as counters, adders,
and multipliers. If required, the designer can also create special-purpose
functions which use a specific LE operating mode for optimal
performance.
The architecture provides a synchronous clock enable to the register in all
four modes. Quartus and MAX+PLUS II software packages can set DATA1
to enable the register synchronously, providing easy implementation of
fully synchronous designs.
Figure 9 shows the LE operating modes.
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EPF10K100BFC256-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC