參數(shù)資料
型號： EP4CGX22CF19I7N
廠商： Altera
文件頁數(shù)： 30/42頁
文件大小： 0K
描述： IC CYCLONE IV GX FPGA 22K 324FBG
產(chǎn)品培訓(xùn)模塊： Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝： 84
系列： CYCLONE® IV GX
LAB/CLB數(shù)： 1330
邏輯元件/單元數(shù)： 21280
RAM 位總計： 774144
輸入/輸出數(shù)： 150
電源電壓： 1.16 V ~ 1.24 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 324-LBGA
供應(yīng)商設(shè)備封裝： 324-FBGA（19x19）
1–36
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
Table 1–44 and Table 1–45 list the IOE programmable delay for Cyclone IV GX
devices.
Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices (1), (2)
Parameter
Paths
Affected
Number
of
Settings
Min
Offset
Max Offset
Unit
Fast Corner
Slow Corner
C6
I7
C6
C7
C8
I7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7
0
1.313
1.209
2.184
2.336
2.451
2.387
ns
Input delay from pin to
input register
Pad to I/O
input register
8
0
1.312
1.208
2.200
2.399
2.554
2.446
ns
Delay from output
register to output pin
I/O output
register to
pad
2
0
0.438
0.404
0.751
0.825
0.886
0.839
ns
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock
network
12
0
0.713
0.682
1.228
1.41
1.566
1.424
ns
Notes to Table 1–44:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Table 1–45. IOE Programmable Delay on Row Pins for Cyclone IV GX Devices (1), (2)
Parameter
Paths
Affected
Number
of
Settings
Min
Offset
Max Offset
Unit
Fast Corner
Slow Corner
C6
I7
C6
C7
C8
I7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7
0
1.314
1.210
2.209
2.398
2.526
2.443
ns
Input delay from pin to
input register
Pad to I/O
input register
8
0
1.313
1.208
2.205
2.406
2.563
2.450
ns
Delay from output
register to output pin
I/O output
register to
pad
2
0
0.461
0.421
0.789
0.869
0.933
0.884
ns
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock network
12
0
0.712
0.682
1.225
1.407
1.562
1.421
ns
Notes to Table 1–45:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software
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