參數(shù)資料
型號(hào)： EP4CGX22CF19I7N
廠商： Altera
文件頁(yè)數(shù)： 13/42頁(yè)
文件大?。?/td> 0K
描述： IC CYCLONE IV GX FPGA 22K 324FBG
產(chǎn)品培訓(xùn)模塊： Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝： 84
系列： CYCLONE® IV GX
LAB/CLB數(shù)： 1330
邏輯元件/單元數(shù)： 21280
RAM 位總計(jì)： 774144
輸入/輸出數(shù)： 150
電源電壓： 1.16 V ~ 1.24 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 324-LBGA
供應(yīng)商設(shè)備封裝： 324-FBGA（19x19）
1–20
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
PLD-Transceiver Interface
Interface speed
(F324 and smaller
package)
—
25
—
125
25
—
125
25
—
125
MHz
Interface speed
(F484 and larger
package)
—
25
—
156.25
25
—
156.25
25
—
156.25
MHz
Digital reset pulse
width
—
Minimum is 2 parallel clock cycles
Notes to Table 1–21:
(1) This specification is valid for transmitter output jitter specification with a maximum total jitter value of 112 ps, typically for 3.125 Gbps SRIO and XAUI
protocols.
(2) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk frequency
is 37.5 MHz if the transceiver channel is configured in Receiver Only or Receiver and Transmitter mode.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The rate matcher supports only up to ±300 parts per million (ppm).
(5) Supported for the N148, F169, and F324 device packages only.
(6) Supported for the F484, F672, and F896 device packages only. Pending device characterization.
(7) To support CDR ppm tolerance greater than ±300 ppm, implement ppm detector in user logic and configure CDR to Manual Lock Mode.
(8) Asynchronous spread-spectrum clocking is not supported.
(9) For the EP4CGX30 (F484 package only), EP4CGX50, and EP4CGX75 devices, the CDR ppl tolerance is ±200 ppm.
(10) Time taken until pll_locked goes high after pll_powerdown deasserts.
(11) Time that the CDR must be kept in lock-to-reference mode after rx_analogreset deasserts and before rx_locktodata is asserted in manual mode.
(12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode (Figure 1–2), or after rx_freqlocked signal goes high in
automatic mode (Figure 1–3).
(13) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode.
(14) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode.
(15) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 4 of 4)
Symbol/
Description
Conditions
C6
C7, I7
C8
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
相關(guān)PDF資料
PDF描述
EP4CGX22CF19C6N IC CYCLONE IV GX FPGA 22K 324FBG
A3P1000-FG484 IC FPGA 1KB FLASH 1M 484-FBGA
M1A3P1000-FG484 IC FPGA M1 1KB FLASH 1M 484FBGA
M1A3P1000-FGG484 IC FPGA M1 1KB FLASH 1M 484FBGA
APA075-FGG144I IC FPGA PROASIC+ 75K 144-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4CGX22F17C8 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet
EP4CGX22F23C8N 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview
EP4CGX22F23I7N 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet
EP4CGX30 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview
EP4CGX30BF14C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV GX 1840 LABs 72 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*