參數(shù)資料
型號(hào)： EP4CGX22CF19I7N
廠商： Altera
文件頁數(shù)： 27/42頁
文件大?。?/td> 0K
描述： IC CYCLONE IV GX FPGA 22K 324FBG
產(chǎn)品培訓(xùn)模塊： Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝： 84
系列： CYCLONE® IV GX
LAB/CLB數(shù)： 1330
邏輯元件/單元數(shù)： 21280
RAM 位總計(jì)： 774144
輸入/輸出數(shù)： 150
電源電壓： 1.16 V ~ 1.24 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 324-LBGA
供應(yīng)商設(shè)備封裝： 324-FBGA（19x19）
Chapter 1: Cyclone IV Device Datasheet
1–33
Switching Characteristics
December 2013
Altera Corporation
f For more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to Section III: System
Performance Specifications of the External Memory Interface Handbook.
Table 1–37 lists the memory output clock jitter specifications for Cyclone IV devices.
Duty Cycle Distortion Specifications
Table 1–38 lists the worst case duty cycle distortion for Cyclone IV devices.
OCT Calibration Timing Specification
Table 1–39 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone IV devices.
Table 1–37. Memory Output Clock Jitter Specifications for Cyclone IV Devices (1), (2)
Parameter
Symbol
Min
Max
Unit
Clock period jitter
tJIT(per)
–125
125
ps
Cycle-to-cycle period jitter
tJIT(cc)
–200
200
ps
Duty cycle jitter
tJIT(duty)
–150
150
ps
Notes to Table 1–37:
(1) Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2
standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL
output routed on a global clock (GCLK) network.
Table 1–38. Duty Cycle Distortion on Cyclone IV Devices I/O Pins (1), (2), (3)
Symbol
C6
C7, I7
C8, I8L, A7
C9L
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output Duty Cycle
4555
%
Notes to Table 1–38:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general
purpose I/O pins.
(2) Cyclone IV devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current
strength.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–39. Timing Specification for Series OCT with Calibration at Device Power-Up for
Cyclone IV Devices (1)
Symbol
Description
Maximum
Units
tOCTCAL
Duration of series OCT with
calibration at device power-up
20
s
Note to Table 1–39:
(1) OCT calibration takes place after device configuration and before entering user mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4CGX22F17C8 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet
EP4CGX22F23C8N 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview
EP4CGX22F23I7N 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet
EP4CGX30 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview
EP4CGX30BF14C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 1840 LABs 72 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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