參數(shù)資料
型號: M1A3P1000-FG484
廠商: Microsemi SoC
文件頁數(shù): 1/12頁
文件大小: 0K
描述: IC FPGA M1 1KB FLASH 1M 484FBGA
標準包裝: 40
系列: ProASIC3
RAM 位總計: 147456
輸入/輸出數(shù): 300
門數(shù): 1000000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應商設備封裝: 484-FPBGA(23x23)
December 2008
1
2008 Actel Corporation
See Actel’s website for the latest version of the datasheet
Prod uct B r i e f
ARM CortexTM-M1
Product Summary
Key Features
Designed Specifically for Implementation in FPGAs
32-Bit RISC Architecture (ARMv6-M)
32-Bit AHB-Lite Bus Interface
3-Stage Pipeline
32-Bit ALU
32-Bit Memory Addressing Range
Embedded ICE-RT Real-Time Debug Unit
JTAG Interface Unit
Intended Use
MicroTCA
System Management
Avionics
Robotics
Medical Equipment
Automotive Infotainment
Personal Media Players
Wireless Handsets
Digital Still Cameras
Benefits
Fully Implemented in FPGA Fabric
User Can Access All Core Signals and I/Os
User Can Program into FPGA
No License Fees or Royalties
Can Run All Existing Thumb Code
Upward Compatible with Cortex-M3
Supported Families
IGLOO (M1AGL)
IGLOOe (M1AGLE)
ProASIC3L (M1A3PXXXXL)
ProASIC3 (M1A3P)
ProASIC3E (M1A3PE)
Fusion (M1AFS)
Synthesis and Simulation support
Directly
Supported
within
the
Actel
Libero
Integrated Design Environment (IDE)
Synthesis: Synplify and Design Compiler
Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
Verification and Compliance
Compliant
with
ARMv6-M
(ARM
Cortex-M1)
Instruction Set Architecture (ISA)
Introduction
The Cortex-M1 soft IP core is a member of the ARM
Cortex family of processors and has been optimized for
use in Actel ARM-enabled FPGAs. Refer to the ARM
Cortex-M1 Handbook for detailed information on the
Cortex-M1.
The ARM Cortex-M1 is supplied with an AMBA AHB-Lite
interface for inclusion in an AMBA-based processor
system such as the one generated by the Actel
CoreConsole IP deployment platform.
Cortex-M1 Processor
ARM
Cortex-M1
is
a
general
purpose,
32-bit
microprocessor that offers high performance and small
size in FPGAs. ARM Cortex-M1 runs a subset of the
Thumb-2 instruction set (ARMv6-M), which includes all
base 16-bit Thumb instructions and a few Thumb-2 32-bit
instructions (BL, MRS, MSR, ISB, DSB, and DMB). This
enables very tight and efficient code to be written for
the processor that is ideal for the limited memory
typically found in embedded applications.
The main blocks in ARM Cortex-M1 are the processor
core, the Nested Vectored Interrupt Controller (NVIC),
the AHB interface, and the debug unit. The processor
core supports 13 general purpose 32-bit registers,
including the Link Register (LR), Program Counter (PC),
Program Status Register (xPSR), and two banked Stack
Pointers (SP).
Prod uct B r i e f
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