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鍨嬭櫉锛� EP2S60F672C4
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 59/768闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC STRATIX II FPGA 60K 672-FBGA
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Three Reasons to Use FPGA's in Industrial Designs
妯欐簴鍖呰锛� 10
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 3022
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 60440
RAM 浣嶇附瑷堬細 2544192
杓稿叆/杓稿嚭鏁�(sh霉)锛� 492
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
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灏佽/澶栨锛� 672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 672-BGA锛�27x27锛�
閰嶇敤锛� 544-1700-ND - DSP KIT W/STRATIX II EP2S60N
544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛� 544-1127
EP2S60F672C4ES
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Altera Corporation
5鈥�5
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
VOL
Low-level output voltage
IOL = 4 mA (2)
0.45
V
Notes to Tables 5鈥�5:
(1)
Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
(2)
This specification is supported across all the programmable drive strength settings available for this I/O standard
as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5鈥�6. LVCMOS Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCIO (1)
Output supply voltage
3.135
3.465
V
VIH
High-level input voltage
1.7
4.0
V
VIL
Low-level input voltage
鈥�0.3
0.8
V
VOH
High-level output voltage
VCCIO = 3.0,
IOH = 鈥�0.1 mA (2)
VCCIO 鈥� 0.2
V
VOL
Low-level output voltage
VCCIO = 3.0,
IOL = 0.1 mA (2)
0.2
V
Notes to Table 5鈥�6:
(1)
Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
(2)
This specification is supported across all the programmable drive strength available for this I/O standard as
shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5鈥�7. 2.5-V I/O Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCIO (1)
Output supply voltage
2.375
2.625
V
VIH
High-level input voltage
1.7
4.0
V
VIL
Low-level input voltage
鈥�0.3
0.7
V
VOH
High-level output voltage
IOH = 鈥�1mA (2)
2.0
V
VOL
Low-level output voltage
IOL = 1 mA (2)
0.4
V
Notes to Table 5鈥�7:
(1)
Stratix II devices VCCIO voltage level support of 2.5 卤 -5% is narrower than defined in the Normal Range of the
EIA/JEDEC standard.
(2)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5鈥�5. LVTTL Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
鐩搁棞(gu膩n)PDF璩囨枡
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EP2S60F672C5 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672C5N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672I4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672I4N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256