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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S60F672C4
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 331/768闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC STRATIX II FPGA 60K 672-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 3022
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 60440
RAM 浣嶇附瑷堬細 2544192
杓稿叆/杓稿嚭鏁�(sh霉)锛� 492
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 672-BGA锛�27x27锛�
閰嶇敤锛� 544-1700-ND - DSP KIT W/STRATIX II EP2S60N
544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛� 544-1127
EP2S60F672C4ES
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Altera Corporation
3鈥�1
January 2008
3. External Memory
Interfaces in Stratix II and
Stratix II GX Devices
Introduction
Stratix II and Stratix II GX devices support a broad range of external
memory interfaces such as double data rate (DDR) SDRAM, DDR2
SDRAM, RLDRAM II, QDRII SRAM, and single data rate (SDR) SDRAM.
Its dedicated phase-shift circuitry allows the Stratix II or Stratix II GX
device to interface with an external memory at twice the system clock
speed (up to 300 MHz/600 megabits per second (Mbps) with
RLDRAM II). In addition to external memory interfaces, you can also use
the dedicated phase-shift circuitry for other applications that require a
shifted input signal.
Typical I/O architectures transmit a single data word on each positive
clock edge and are limited to the associated clock speed. To achieve a
400-Mbps transfer rate, a SDR system requires a 400-MHz clock. Many
new applications have introduced a DDR I/O architecture as an
alternative to SDR architectures. While SDR architectures capture data on
one edge of a clock, the DDR architectures captures data on both the
rising and falling edges of the clock, doubling the throughput for a given
clock frequency and accelerating performance. For example, a 200-MHz
clock can capture a 400-Mbps data stream, enhancing system
performance and simplifying board design.
Most new memory architectures use a DDR I/O interface. Although
Stratix II and Stratix II GX devices also support the mature and well
established SDR external memory, this chapter focuses on DDR memory
standards. These DDR memory standards cover a broad range of
applications for embedded processor systems, image processing, storage,
communications, and networking.
Stratix II devices offer external memory support in every I/O bank. The
side I/O banks support the PLL-based interfaces running at up to
200 MHz, while the top and bottom I/O banks support PLL- and
DLL-based interfaces. Figure 3鈥�1 shows Stratix II device memory
support.
SII52003-4.5
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
EP2AGX125DF25C5 IC ARRIA II GX FPGA 125K 572FBGA
EP2AGX95EF35I5N IC ARRIA II GX FPGA 95K 1152FBGA
EP2AGX95EF35C4N IC ARRIA II GX FPGA 95K 1152FBGA
EP2AGX95EF29I3N IC ARRIA II GX FPGA 95K 780FBGA
EP1S40F1508C7N IC STRATIX FPGA 40K LE 1508-FBGA
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EP2S60F672C5 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672C5N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672I4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672I4N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256