fHSDR
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S60F672C4
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 151/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 60K 672-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 3022
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 60440
RAM 浣嶇附瑷�(j矛)锛� 2544192
杓稿叆/杓稿嚭鏁�(sh霉)锛� 492
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 672-BGA锛�27x27锛�
閰嶇敤锛� 544-1700-ND - DSP KIT W/STRATIX II EP2S60N
544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛� 544-1127
EP2S60F672C4ES
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�绗�756闋�绗�757闋�绗�758闋�绗�759闋�绗�760闋�绗�761闋�绗�762闋�绗�763闋�绗�764闋�绗�765闋�绗�766闋�绗�767闋�绗�768闋�
5鈥�88
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
High-Speed I/O Specifications
fHSDR (data rate)
J = 4 to 10 (LVDS, HyperTransport technology)
150
1,040
Mbps
J = 2 (LVDS, HyperTransport technology)
760
Mbps
J = 1 (LVDS only)
500
Mbps
fHSDRDPA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
150
1,040
Mbps
TCCS
All differential standards
-
200
ps
SW
All differential standards
330
-
ps
Output jitter
190
ps
Output tRISE
All differential I/O standards
160
ps
Output tFAL L
All differential I/O standards
180
ps
tDUTY
45
50
55
%
DPA run length
6,400
UI
DPA jitter tolerance
Data channel peak-to-peak jitter
0.44
UI
DPA lock time
Standard
Training
Pattern
Transition
Density
Number of
repetitions
SPI-4
0000000000
1111111111
10%
256
Parallel Rapid I/O
00001111
25%
256
10010000
50%
256
Miscellaneous
10101010
100%
256
01010101
256
Notes to Table 5鈥�89:
(1)
When J = 4 to 10, the SERDES block is used.
(2)
When J = 1 or 2, the SERDES block is bypassed.
(3)
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150
鈮� input clock
frequency 脳 W
鈮� 1,040.
(4)
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
Table 5鈥�89. High-Speed I/O Specifications for -3 Speed Grade (Part 2 of 2)
Notes (1), (2)
Symbol
Conditions
-3 Speed Grade
Unit
Min
Typ
Max
鐩搁棞(gu膩n)PDF璩囨枡
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EP2S60F672C5 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672C5N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672I4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F672I4N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256