參數(shù)資料
型號： EP2AGX95EF35I3
廠商： Altera
文件頁數(shù)： 83/90頁
文件大?。?/td> 0K
描述： IC ARRIA II GX FPGA 95K 1152FBGA
標(biāo)準(zhǔn)包裝： 3
系列： Arria II GX
LAB/CLB數(shù)： 3747
邏輯元件/單元數(shù)： 89178
RAM 位總計： 6839296
輸入/輸出數(shù)： 452
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1152-BBGA
供應(yīng)商設(shè)備封裝： 1152-FBGA（27x27）
1–76
Chapter 1: Device Datasheet for Arria II Devices
Glossary
December 2013
Altera Corporation
S
SW (sampling
window)
The period of time during which the data must be valid in order to capture it correctly. The setup
and hold times determine the ideal strobe position within the sampling window:
Timing Diagram
Single-ended
Voltage
Referenced I/O
Standard
The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver
changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing:
Single-Ended Voltage Referenced I/O Standard
T
tC
High-speed receiver and transmitter input and output clock period.
TCCS
(channel-to-
channel-
skew)
The timing difference between the fastest and slowest output edges, including tCO variation and
clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under S in this table).
tDUTY
High-speed I/O block: Duty cycle on the high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input.
tOUTPJ_IO
Period jitter on the general purpose I/O driven by a PLL.
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL.
tRISE
Signal low-to-high transition time (20-80%).
Table 1–68. Glossary (Part 3 of 4)
Letter
Subject
Definitions
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2AGX95EF35I3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 3747 LABs 452 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX95EF35I5 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 3747 LABs 452 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX95EF35I5ES 制造商:Altera Corporation 功能描述:FPGA Arria
EP2AGX95EF35I5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 3747 LABs 452 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGXF35NAH 制造商:Altera Corporation 功能描述:
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