參數(shù)資料
型號： EP20K30E
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁數(shù)： 55/117頁
文件大?。?/td> 570K
代理商： EP20K30E
Altera Corporation
55
APEX 20K Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
All APEX 20K devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
APEX 20K devices can also use the JTAG port for configuration with the
Quartus II software or with hardware using either Jam Files (
.jam
) or Jam
Byte-Code Files (
.jbc
). Finally, APEX 20K devices use the JTAG port to
monitor the logic operation of the device with the SignalTap embedded
logic analyzer. APEX 20K devices support the JTAG instructions shown in
Table 19
. Although EP20K1500E devices support the JTAG BYPASS and
SignalTap instructions, they do not support boundary-scan testing or the
use of the JTAG port for configuration.
Note to
Table 19
:
(1)
The EP20K1500E device supports the JTAG BYPASS instruction and the SignalTap instructions.
Table 19. APEX 20K JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device
pins. Also used by the SignalTap embedded logic analyzer.
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the BST
data to pass synchronously through selected devices to adjacent devices during
normal device operation.
Selects the 32-bit USERCODE register and places it between the
TDI
and
TDO
pins,
allowing the USERCODE to be serially shifted out of
TDO
.
Selects the IDCODE register and places it between
TDI
and
TDO
, allowing the
IDCODE to be serially shifted out of
TDO
.
Used when configuring an APEX 20K device via the JTAG port with a MasterBlaster
TM
or ByteBlasterMV
TM
download cable, or when using a Jam File or Jam Byte-Code File
via an embedded processor.
Monitors internal device operation with the SignalTap embedded logic analyzer.
EXTEST
BYPASS
(1)
USERCODE
IDCODE
ICR Instructions
SignalTap Instructions
(1)
相關(guān)PDF資料
PDF描述
EP20K400 Programmable Logic Device Family
EP20K400E Programmable Logic Device Family
EP20K600E Programmable Logic Device Family
EP20K60E Programmable Logic Device Family
EP220 Classic EPLDs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K30EFC144-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 192 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K30EFC144-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K30EFC144-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 192 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K30EFC144-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 192 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K30EFC144-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 192 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*