參數(shù)資料
型號： EP20K200FC484-3V
廠商： Altera
文件頁數(shù)： 42/117頁
文件大小： 0K
描述： IC APEX 20KE FPGA 200K 484-BGA
標準包裝： 60
系列： APEX-20K®
LAB/CLB數(shù)： 832
邏輯元件/單元數(shù)： 8320
RAM 位總計： 106496
輸入/輸出數(shù)： 382
門數(shù)： 404000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FBGA（23x23）
30
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
ESBs can implement synchronous RAM, which is easier to use than
asynchronous RAM. A circuit using asynchronous RAM must generate
the RAM write enable (WE) signal, while ensuring that its data and address
signals meet setup and hold time specifications relative to the WE signal.
In contrast, the ESB’s synchronous RAM generates its own WE signal and
is self-timed with respect to the global clock. Circuits using the ESB’s self-
timed RAM must only meet the setup and hold time specifications of the
global clock.
ESB inputs are driven by the adjacent local interconnect, which in turn can
be driven by the MegaLAB or FastTrack Interconnect. Because the ESB can
be driven by the local interconnect, an adjacent LE can drive it directly for
fast memory access. ESB outputs drive the MegaLAB and FastTrack
Interconnect. In addition, ten ESB outputs, nine of which are unique
output lines, drive the local interconnect for fast connection to adjacent
LEs or for fast feedback product-term logic.
When implementing memory, each ESB can be configured in any of the
following sizes: 128
× 16, 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1. By
combining multiple ESBs, the Quartus II software implements larger
memory blocks automatically. For example, two 128
× 16 RAM blocks can
be combined to form a 128
× 32 RAM block, and two 512 × 4 RAM blocks
can be combined to form a 512
× 8 RAM block. Memory performance does
not degrade for memory blocks up to 2,048 words deep. Each ESB can
implement a 2,048-word-deep memory; the ESBs are used in parallel,
eliminating the need for any external control logic and its associated
delays.
To create a high-speed memory block that is more than 2,048 words deep,
ESBs drive tri-state lines. Each tri-state line connects all ESBs in a column
of MegaLAB structures, and drives the MegaLAB interconnect and row
and column FastTrack Interconnect throughout the column. Each ESB
incorporates a programmable decoder to activate the tri-state driver
appropriately. For instance, to implement 8,192-word-deep memory, four
ESBs are used. Eleven address lines drive the ESB memory, and two more
drive the tri-state decoder. Depending on which 2,048-word memory
page is selected, the appropriate ESB driver is turned on, driving the
output to the tri-state line. The Quartus II software automatically
combines ESBs with tri-state lines to form deeper memory blocks. The
internal tri-state control logic is designed to avoid internal contention and
floating lines. See Figure 18.
相關(guān)PDF資料
PDF描述
EP20K200EFI672-2X IC APEX 20KE FPGA 200K 672-FBGA
EP20K100QC240-3V IC APEX 20K FPGA 100K 240-PQFP
EP20K100QC208-3V IC APEX 20K FPGA 100K 208-PQFP
EP20K100EBI356-2X IC APEX 20KE FPGA 100K 356-BGA
ABB65DHAN CONN EDGECARD 130PS R/A .050 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K200FI484-1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K200FI484-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K200FI484-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K200FI484-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K200FI484-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 832 Macro 382 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*