參數(shù)資料
型號(hào)： EP20K1500E
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁數(shù)： 72/117頁
文件大小： 570K
代理商： EP20K1500E
72
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Figure 40. Synchronous Bidirectional Pin External Timing
Notes to
Figure 40
:
(1)
The output enable and input registers are LE registers in the LAB adjacent to a
bidirectional row pin. The output enable register is set with “Output Enable
Routing= Signal-Pin” option in the Quartus II software.
(2)
The LAB adjacent input register is set with “Decrease Input Delay to Internal Cells=
Off”. This maintains a zero hold time for lab adjacent registers while giving a fast,
position independent setup time. A faster setup time with zero hold time is possible
by setting “Decrease Input Delay to Internal Cells= ON” and moving the input
register farther away from the bidirectional pin. The exact position where zero hold
occurs with the minimum setup time, varies with device density and speed grade.
Table 31
describes the
f
MAX
timing parameters shown in
Figure 36 on
page 68
.
PRN
CLRN
D
Q
PRN
CLRN
D
Q
(1)
IOE Register
Bidirectional Pin
Dedicated
Clock
PRN
CLRN
D
Q
(1)
XZBIDIR
t
ZXBIDIR
t
OUTCOBIDIR
t
INSUBIDIR
t
INHBIDIR
t
OE Register
Output IOE Register
Input Register
(2)
Table 31. APEX 20K f
MAX
Timing Parameters
(Part 1 of 2)
Symbol
Parameter
t
SU
t
H
t
CO
t
LUT
t
ESBRC
t
ESBWC
t
ESBWESU
t
ESBDATASU
t
ESBDATAH
t
ESBADDRSU
t
ESBDATACO1
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LUT delay for data-in
ESB Asynchronous read cycle time
ESB Asynchronous write cycle time
ESB WE setup time before clock when using input register
ESB data setup time before clock when using input register
ESB data hold time after clock when using input register
ESB address setup time before clock when using input registers
ESB clock-to-output delay when using output registers
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K1500EBC652-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1500EBC652-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K1500EBC652-1X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1500EBC652-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1500EBC652-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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