參數(shù)資料
型號(hào)： EP20K1500E
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁數(shù)： 54/117頁
文件大?。?/td> 570K
代理商： EP20K1500E
54
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Notes to
Tables 17
and
18
:
(1)
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(2)
The maximum lock time is 40 μs or 2000 input clock cycles, whichever occurs first.
(3)
Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs are still
disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins
once the
CLKLK_ENA
pin goes high in user mode.
(4)
The PLL VCO operating range is 200 MHz e f
VCO
e 840 MHz for LVDS mode.
SignalTap
Embedded
Logic Analyzer
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process can be difficult after a board is designed and
manufactured.
APEX 20K devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX 20K
device provides the ability to monitor design operation over a period of
time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze
f
IN
Input clock frequency
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
GTL+
SSTL-2 Class
I
SSTL-2 Class
II
SSTL-3 Class
I
SSTL-3 Class
II
LVDS
1.5
1.5
1.5
1.5
1.5
290
281
272
303
291
1.5
1.5
1.5
1.5
1.5
257
250
243
261
253
MHz
MHz
MHz
MHz
MHz
1.5
291
1.5
253
MHz
1.5
300
1.5
260
MHz
1.5
300
1.5
260
MHz
1.5
420
1.5
350
MHz
Table 18. APEX 20KE Clock Input & Output Parameters
(Part 2 of 2)
Note (1)
Symbol
Parameter
I/O Standard
-1X Speed Grade
-2X Speed Grade
Units
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
EP20K160E Programmable Logic Device Family
EP20K200 Programmable Logic Device Family
EP20K200E Programmable Logic Device Family
EP20K300E Programmable Logic Device Family
EP20K30E Programmable Logic Device Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K1500EBC652-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1500EBC652-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K1500EBC652-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1500EBC652-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1500EBC652-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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