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參數(shù)資料
| 型號： | EP1M120FC484-5 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, PBGA484 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484 |
| 文件頁數(shù)： | 2/84頁 |
| 文件大?。?/td> | 936K |
| 代理商： | EP1M120FC484-5 |
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10
Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 3. Transmitter Diagram for Source Synchronous Mode
Notes:
(1)
EP1M350 devices have 18 individual transmitter channels. EP1M120 devices have 8 individual transmitter
channels.
(2)
W = 1 to 12, 14, 16, 18, or 20
B = 1 to 12, 14, 16, 18, or 20
J = 4, 7, 8, 9 to 12, 14, 16, 18, or 20
W, B, and J do not have to be equal.
(3)
This clock pin drives an HSDI PLL only. It does not drive to the core.
In CDR mode, serial data is supported up to 1.25 Gbps per channel. The
system provides a reference clock which is multiplied by the receiver or
transmitter PLL to the same rate as the data is provided. For the receiver,
this multiplied reference clock is used by a CRU on each receiver channel
to generate a recovered clock in-phase with the received data. That
recovered clock drives the programmable deserializer and synchronizer.
The synchronizer is a FIFO for data transfer between the recovered clock
domain and the global clock domain. The dedicated synchronizers can be
bypassed if necessary. See Figure 4.
The multiplied reference clock is also used to synchronize and serialize at
the transmitter side.
Transmitter
Channel
HSDI_CLK1 (3)
Global Clock
from Receiver
or System Clock
HSDI
PLL1
×W
×
1
J
Serializer
Data from
LEs
Transmitter Channel 1
J Bits Wide
Transmitter
Channel
Transmitter Channel 2
Transmitter
Channel
Transmitter Channel 8
TXOUTCLOCK
W
B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1M350 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet |
| EP1M350F780C5 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - MERCURY 1440 LABs 486 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1M350F780C6 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - MERCURY 1440 LABs 486 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1M350F780C7 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - MERCURY 1440 LABs 486 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1M350F780I6 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - MERCURY 1440 LABs 486 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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