參數(shù)資料
型號(hào)： ELANSC410-66AI
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
中文描述： 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PBGA292
封裝： PLASTIC, BGA-292
文件頁數(shù)： 75/132頁
文件大?。?/td> 2400K
代理商： ELANSC410-66AI
élanSC400 and élanSC410 Microcontrollers Data Sheet
75
CFG3 Pin
This configuration pin is used for selecting between the
GPIO_CS4–GPIO_CS2 I/O pins and the SD bus buffer
control signals: DBUFOE, DBUFRDL, and DBUFRDH.
When the buffer control signal configuration is selected
using the CFG3 pin, the DBUFOE, DBUFRDL, and
DBUFRDH signals are driven from boot time on for all
accesses to the peripheral data bus. These signals are
used for the external system bus transceiver control.
See Table 24 for the CFG3 configuration definitions.
BNDSCN_EN Pin
The BNDSCN_EN configuration pin (see Table 25) is
used to enable the boundary scan function I/O pins.
The following pins are configured for their boundary
scan function when BNDSCN_EN is asserted:
I
BNDSCN_TCK
I
BNDSCN_TMS
I
BNDSCN_TDI
I
BNDSCN_TDO
Table 24.
CFG3 Configuration
CFG3
0
Configuration
Enables the GPIO_CS4–GPIO_CS2 signals
on the I/O pins
Enables the SD bus buffer control signals
DBUFOE, DBUFRDL, and DBUFRDH
on the I/O pins
1
Table 25.
BNDSCN_EN Configuration
BNDSCN_EN
0
1
Configuration
Enables the PC Card function
Enables the boundary scan functions:
BNDSCN_TCK, BNDSCN_TMS,
BNDSCN_TDI, and BNDSCN_TDO
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