參數(shù)資料
型號： ELANSC410-66AI
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
中文描述： 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PBGA292
封裝： PLASTIC, BGA-292
文件頁數(shù)： 128/132頁
文件大小： 2400K
代理商： ELANSC410-66AI
128
élanSC400 and élanSC410 Microcontrollers Data Sheet
Figure 63.
Graphics Panel Interface
Timing (élanSC400 Microcontroller Only)
Table 51.
LCD Graphics Controller Cycles—élanSC400 Microcontroller Only
Symbol
Parameter Description
Notes
33-MHz
External Bus
Min
4T
2T
T
T
T-15
T-15
8T
Unit
Max
t1a
t1b
t2
t3
t4
t5
t6
t7
t8
t9
t11a
t11b
t12a
t12b
t13
t14
t15
SCK period, monochrome panel
SCK period, color STN panel
SCK High time
SCK Low time
Setup, data to SCK falling edge
Hold, LCD_data from SCK falling edge
Width, LC
Setup, FRM to LC falling
Hold, FRM from LC falling
Delay, LC falling to M phase change
Delay, power-on sequencing, LVDD to signals
Delay, power-on sequencing, signals to LVEE
Delay, power-off sequencing, LVEE to signals, normal power-down
Delay, power-off sequencing, signals to LVDD, normal power-down
Delay, LVEE to LCD_SIGNALS off, emergency power-down
Delay, LCD_SIGNALS off to LVDD off, emergency power-down
Delay, emergency power-off sequencing from BL2 edge
1
Notes:
1.
T = period of internal video dot clock—programmable via the Pixel Clock Control Register.
2. Programmable to within resolution of 8T intervals (single-screen mode) or 16T intervals (dual-screen mode).
3. Programmable through PMU Control Register 1, bits 2–0.
4. Programmable through PMU Control Register 1, bits 5–3.
5. Programmable through PMU Control Register 2, bits 2–0.
6. Programmable through PMU Control Register 2, bits 5–3.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ms
ns
ns
μ
s
1
1
1
1
1
1,2
1,2
0
15
62.5
62.5
500
500
3
7.8
7.8
62.5
62.5
0
0
0
4
5
6
10
t2
t4
t5
t1a,b
t6
t7
t8
t9
t3
SCK
LCDD7–
LCDD0
LC
FRM
M
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