參數(shù)資料
型號: ELANSC410-66AI
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
中文描述: 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PBGA292
封裝: PLASTIC, BGA-292
文件頁數(shù): 113/132頁
文件大小: 2400K
代理商: ELANSC410-66AI
élanSC400 and élanSC410 Microcontrollers Data Sheet
113
Table 40.
Parallel Port Cycles
1
Notes:
1. The signal names used in Figure 48 and Figure 49 are the PC/AT Compatible and Bidirectional mode signal names.
2. During EPP mode and Bidirectional mode, PPDWE acts as the parallel port chip select and is asserted for both reads and
writes. For PC/AT Compatible mode, PPDWE will be asserted only for parallel port write cycles.
3. These timings are only valid for EPP mode.
4. BUSY is asserted to add wait states to the parallel port access.
5. DBUFOE and DBUFRDL may be required when using the VESA local bus interface or a x32 DRAM interface.
Symbol
Parameter Description
Notes
33-MHz
External Bus
Min
2
2
2
2
50
50
Unit
Max
20
20
20
20
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
PPDWE delay from IOW
PPOEN delay from IOW
STRB delay from IOW
SLCTIN, AFDT valid from IOW
SD setup to IOW
SD hold from IOW
BUSY asserted from IOW asserted
IOW deasserted from BUSY deasserted
IOW pulse width
SLCTIN, AFDT recovery
DBUFOE setup to IOW
DBUFOE hold from IOW
PPDWE delay from IOR
SLCTIN, AFDT valid from IOR
SD setup to IOR deasserted
SD hold from IOR
BUSY asserted from IOR asserted
IOR deasserted from BUSY deasserted
IOR pulse width
DBUFOE, DBUFRDL setup to IOR
DBUFOE, DBUFRDL hold from IOR
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
300
4
100
450
1000
20
20
2
2
20
0
5
5
2
20
20
3
4
300
4
100
450
0
10
5
5
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