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參數(shù)資料
| 型號： | ELANSC300-25VI |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 58/139頁 |
| 文件大小： | 1388K |
| 代理商： | ELANSC300-25VI |
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58
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
The type of Micro Power DRAM refresh performed
(CAS-before-RAS refresh, or self refresh) will be the
same as that for which the part was configured before
the IORESET pin sampled Low. If the micro power re-
fresh feature is enabled for CAS-before-RAS refresh,
the system designer should maintain power on the
VMEM power pin of the élanSC300 microcontroller
and not remove power from the DRAM devices. If the
micro power refresh feature is enabled for self refresh,
the system designer may or may not be required to
maintain power on the VMEM power pin of the
élanSC300 microcontroller, depending on the specific
requirement of the DRAM device in Self-Refresh mode.
Power should not be removed from the DRAM device
itself in either case.
The Micro Power Refresh bit will always be cleared
whenever the RESIN input is sampled Low. Therefore,
when the core is initially powered up, the Micro Power
DRAM refresh feature will be disabled. This bit is unaf-
fected by the IORESET input. This bit will provide the
system BIOS with a mechanism to determine whether
or not the system DRAM data has been retained after
a reset (IORESET) has occurred.
If Self-Refresh mode is selected and enabled for Micro
Power Off mode, then when Micro Power Off mode is
exited, the élanSC300 microcontroller will properly
force a CAS-before-RAS refresh cycle to cause the
DRAMs to exit the Self-Refresh mode. The élanSC300
microcontroller then transitions to the normal CAS-be-
fore-RAS refresh mode. This functionality is exactly the
same as the Self-Refresh mode exit when the CPU
Clock Stopped mode is exited. The élanSC300 micro-
controller generates one CAS-before-RAS refresh
cycle to force the DRAM to exit the Self-Refresh mode.
This is also true for the Micro Power DRAM refresh fea-
ture.
The timing diagrams in Figure 34 and Figure 35, on
page 101, show the sequence required to guarantee a
proper transition into the Micro Power state. This se-
quence is especially critical when the DRAM refresh
option is selected. Note that the power pins of the
élanSC300 microcontroller must be kept stable for
some time after the IORESET input has gone active.
“Stable” means that these power pins should remain at
least at their VCC (min) value for the specified time in-
dicated in Table 51 on page 99.
RESIN and IORESET
The élanSC300 microcontroller has two reset inputs to
support the Micro Power Off mode. These two inputs
are RESIN and IORESET. If Micro Power off mode is
not to be used, the system designer should drive these
two inputs from a common power-on reset source.
Note that the RESIN signal is a 3.3-V only input and is
not 5-V safe. For more information, see Table 24 on
page 59.
RSTDRV Signal Timing
RSTDRV is High True output of the élanSC300 micro-
controller and is a function of the internal core’s reset
state, the state of the
RESIN
and
IORESET
signals, and
the value for the PLL start-up timer in the Clock Control
Register (Index 8Fh). (See “Loop Filters” on page 97
for more information.) RSTDRV indicates that the PLLs
are gated off from the core and prevents the CPU from
executing instructions until the PLL outputs have stabi-
lized.
RSTDRV is asserted immediately whenever VCC
power is applied and either
RESIN
or
IORESET
is as-
serted. The pulse width of RSTDRV may vary and is
determined by the PLL start-up timer and whether or
not
IORESET
and/or
RESIN
is deasserted (i.e., cold boot
versus warm reset or Micro Power Off mode exit).
On a cold boot, when
RESIN
is asserted while power is
applied to the VCC inputs and then deasserted after
time delay (t1), the RSTDRV is immediately asserted
when power is applied, and then held True until
RESIN
and
IORESET
are deasserted. Because the assertion of
RESIN
causes all the configuration registers to be reset
to their default values, the PLL start-up time value in
the Clock Control Register is set to 4 ms and is insuffi-
cient time for the PLLs to start up. This is why the VCC-
to-RESIN timing specification (t1) of 1 second is re-
quired to allow sufficient time for the crystal and the
PLLs to power up and stabilize before
RESIN
and
IORE-
SET
allow RSTDRV to be deasserted.
On a warm reset, the power stays on and the VCC in-
puts are already powered up while the PLLs are either
powered and running or gated off. RSTDRV is asserted
quickly after
RESIN
is asserted, with the pulse width
also determined by the
RESIN
pulse width, because the
default PLL start-up timer has a value of 4 ms. It is
therefore recommended that the system design guar-
antees at least a minimum
RESIN
pulse width of 250 ms
for warm resets.
On a wake-up from Micro Power Off mode, VCC and
AVCC power to the core is maintained active, and the
Clock Configuration Register value for the PLL start-up
timer is preserved, but power is removed from all the
other VCC inputs, and the PLLs are gated off. RSTDRV
is asserted internally, and the output is driven active as
soon as VSYS is powered up. When
IORESET
is first
asserted to go into Micro Power Off Mode, RSTDRV is
immediately asserted High. When power is removed
from the VSYS input (which is also VCCIO for RST-
DRV), the voltage level of RSTDRV begins to decay at
the same rate as VSYS until it reaches approximately
0.7 V, where it remains while in Micro Power Off mode.
This indicates that RSTDRV is still asserted internally
inside the microcontroller and is attempting to drive the
external pin High, but is unable to without power ap-
plied to its I/O driver. When exiting Micro Power Off
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