參數(shù)資料
型號: ELANSC300-25KI
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 32-BIT, 25 MHz, MICROCONTROLLER, PQFP208
封裝: SHRINK, PLASTIC, QFP-208
文件頁數(shù): 43/139頁
文件大?。?/td> 1388K
代理商: ELANSC300-25KI
élanSC300 Microcontroller Data Sheet
43
P R E L I M I N A R Y
CPUCLK
CPU 2X Clock (Output)
This is the timing reference for the local bus device.
The high-speed PLL can be programmed to provide
one of the clock frequencies shown on page 53.
CPURDY
386 CPU Ready Signal (Output; Active Low)
This signal shows the current state of the 386 core
CPU’s CPURDY signal.
CPURST
CPU Reset (Output; Active High)
This signal is used to force the local bus device to an
initial condition. It is also used to allow the local bus de-
vice to synchronize to the CPUCLK. This signal is
taken directly from the internal CPU reset.
D/C
Local Bus Data/Control (Output; Active Low)
This signal indicates to the local bus devices that the
current cycle is either a Data cycle or a Control cycle.
A Low on this signal indicates that the current cycle is
a Control cycle.
LDEV
Local Bus Device Select (Input; Active Low)
This signal is used by the local bus devices to signal
that they will respond to the current cycle. If LDEV is
not driven active by the time specified in Table 57 on
page 108, then the cycle defaults to an ISA bus cycle.
LRDY
Local Bus Device Ready (Input; Active Low)
This signal is used by the local bus devices to terminate
the current bus cycle.
M/IO
Local Bus Memory/I/O (Output; Active Low)
This signal indicates to the local bus devices that the
current cycle is either a memory or an I/O cycle. A Low
on this signal indicates that the current cycle is an I/O
cycle.
W/R
Local Bus Write/Read (Output; Active Low)
This signal indicates to the local bus devices that the
current cycle is either a Read or a Write cycle. A Low
on this signal indicates that the current cycle is a Read
cycle.
MAXIMUM ISA BUS INTERFACE
The pins listed below as part of the “ISA Bus Interface”
are only available when the élanSC300 microcontroller
pin configuration is configured to enable the maximum
ISA Bus. When the maximum ISA bus interface is en-
abled, the internal LCD controller and the CPU local
bus interface are disabled. (This mode does not sup-
port master and ISA refresh cycles.)
For more information, see “Maximum ISA Interface ver-
sus Internal LCD Interface” on page 70, Table 37–Table
on page 73, and the élan
TM
SC300 and élan
TM
SC310
Devices’ ISA Bus Anomalies Application Note
, order
#20747.
0WS
Zero Wait State (Input; Active Low)
This input can be driven active by an ISA memory de-
vice to indicate that it can accept a Zero Wait State
memory cycle.
BALE
Bus Address Latch Enable (Output; Active High)
This PC/AT-compatible signal is used by external de-
vices to latch the LA signals for the current cycle.
DACK7, DACK6, DACK5, DACK3, DACK2, DACK1,
DACK0
DMA Acknowledge (Output; Active Low)
DMA acknowledge signals are active Low output pins
that acknowledge their corresponding DMA requests.
Note:
The DACK2 signal is available regardless of the
élanSC300 microcontroller’s bus mode. DACK1 and
DACK5 are also available in the local bus pin configu-
ration.
DRQ7, DRQ6, DRQ5, DRQ3, DRQ2, DRQ1, DRQ0
DMA Request (Input; Active High)
DMA Request signals are asynchronous DMA channel
request inputs used by peripheral devices to gain ac-
cess to a DMA service.
Note:
The DRQ2 signal is available regardless of the
élanSC300 microcontroller’s bus mode. DRQ1 and
DRQ5 are also available in the local bus pin configura-
tion.
IOCHCHK
I/O Channel Check (Input; Active Low)
This is a PC/AT-compatible signal used to generate an
NMI or SMI.
Note:
IOCHCHK is also available in the Local Bus pin
configuration.
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