參數(shù)資料
型號(hào)： ELANSC300-25KI
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述： 32-BIT, 25 MHz, MICROCONTROLLER, PQFP208
封裝： SHRINK, PLASTIC, QFP-208
文件頁數(shù)： 124/139頁
文件大小： 1388K
代理商： ELANSC300-25KI
124
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
Notes:
1. This is the timing when DOSCS is qualified with MEMR or MEMW, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 0).
2. This is the timing when DOSCS is configured as an address decode, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 1).
These timings are based on Index 51h, bit 1 set for 16-bit DOSCS cycles, and required initial programming. The standard DOS
ROM timings are based on the default wait state settings in bits 2 and 3 of the MMS Memory Wait State Register, Index 62h, set
to 4 wait states. The fast DOS ROM timings are based on Index B8h, bit 7 set for DOSCS cycles to run at high-speed with the
default setting in bits 5 and 6 for 4-wait states.
These timings may be modified via the Command Delay Register, Index 60h. (See the
élan
TM
SC310 Microcontroller Program-
mer’s Reference Manual
, order #18470.)
For more information about fast DOS ROM cycles, see the
élan
TM
SC300 and élan
TM
SC310 Devices’ ISA Bus Anomalies Appli-
cation Note
, order #20747. The fast DOS ROM timings shown here also apply to fast BIOS ROM (ROMCS) accesses controlled
by Miscellaneous 5 Register, Index B3h.
Table 66.
DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles (See Figure 49)
Symbol
Parameter Description
Notes
Standard
DOS ROM
Preliminary
Fast DOS
33 MHz
Preliminary
Fast DOS
25 MHz
Preliminary
Units
Min
Max
Min
Max
Min
Max
t1a
t1b
t2a
t2b
t3a
t3b
t4a
t4b
t5a
t5b
t6
t7
t8
t9
t10
t11a
t11b
t12
t13
t14
t15
t16a
t16b
SA stable to DOSCS active
SA stable to DOSCS active
SA hold from DOSCS inactive (write)
SA hold from DOSCS inactive (read)
DOSCS pulse width (read)
DOSCS pulse width(write)
MEMW active to DOSCS active
MEMR active to DOSCS active
DOSCS hold from MEMW inactive
DOSCS hold from MEMR inactive
RDDATA setup to command inactive
RDDATA hold from command inactive
WRDATA setup to command inactive
WRDATA hold from command inactive
DBUFOE active from command
DBUFOE hold from MEMW
DBUFOE hold from MEMR
ENDIRH, ENDIRL setup to MEMR
ENDIRH, ENDIRL hold from MEMR
DOSCS active to command active
DOSCS hold from SA
MEMR pulse width
MEMW pulse width
1
2
1
1
1
1
1
1
1
1
65
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
8
50
0
550
500
15
0
130
100
20
0
250
175
3
4
3
4
3
4
0
0
25
0
400
45
0
0
25
0
120
15
0
0
33
0
160
20
5
5
0
50
–2
50
–4
65
5
550
500
15
–2
15
–4
15
5
130
100
20
0
20
–4
20
5
250
175
2
2
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