29
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H/A)
Fig. 21 Interrupt control
Fig. 22 Structure of interrupt-related registers
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7 b0
b7 b0
b
7
b
0
b7 b0
b7 b0
In
(INTEDGE : address 003A
16
)
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
IN
I
N
I
N
I
N
S
N
T
0
T
1
T
2
T
3
e
r
0
1
o
t
a
a
a
a
l
I
N
S
u
s
c
c
c
c
I
t
t
t
t
O
T
3
e
r
e
d
i
i
i
i
v
v
v
v
e
e
e
e
2
i
a
(
n
l
r
e
e
e
e
/
t
I
/
e
d
d
d
d
I
N
e
O
t
u
g
g
g
g
T
3
r
r
u
2
r
n
e
e
e
e
s
s
s
s
i
e
e
e
e
n
t
t
e
“
l
l
l
l
t
e
e
e
e
e
e
r
r
”
c
c
c
c
r
l
u
w
t
t
t
t
r
e
i
i
i
i
u
c
p
h
o
o
o
o
p
t
t
e
n
n
n
n
t
e
s
d
e
n
b
b
b
b
s
i
i
i
i
o
t
t
t
t
i
a
:
:
/
u
r
c
e
b
i
t
p
i
n
s
s
i
l
r
e
e
c
a
t
d
e
d
)
0
0
1
:
:
F
R
a
i
l
l
i
i
n
n
g
g
e
e
d
d
g
g
e
e
a
a
c
c
t
i
i
v
v
e
e
s
t
Interrupt request register 1
(IREQ1 : address 003C
16
)
INT
0
interrupt request bit
Reserved
INT
1
interrupt request bit
INT
2
interrupt request bit
INT
3
/ Serial I/O2 interrupt request bit
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register 2
(IREQ2 : address 003D
16
)
T
T
S
S
C
C
A
N
i
m
m
e
e
N
N
D
o
e
e
i
a
i
a
T
T
c
t
r
r
l
l
1
2
I
/
I
/
O
O
i
n
i
n
v
e
d
i
i
n
n
1
1
t
t
e
t
t
e
e
r
t
e
e
r
t
(
r
r
r
e
r
r
r
r
r
e
e
r
r
u
u
c
a
u
u
r
t
u
p
p
e
n
p
p
i
n
r
t
t
p
s
t
t
t
n
r
r
t
e
e
i
o
i
e
e
r
r
“
q
q
n
t
q
q
u
0
u
u
n
u
u
p
”
e
e
n
t
e
e
e
t
w
s
s
t
t
t
r
r
b
t
b
e
q
h
e
b
b
r
u
i
i
t
t
i
r
r
i
e
r
t
u
p
i
t
i
t
u
n
p
t
t
r
e
r
e
q
q
u
u
e
e
s
s
t
t
b
b
i
t
i
t
m
r
r
e
s
i
R
0
R
1
o
n
u
s
s
s
r
e
r
s
e
t
a
b
d
i
)
t
0 : No interrupt request issued
1 : Interrupt request issued
In
(I
C
t
e
O
r
r
N
u
p
1
t
:
c
a
o
d
n
d
t
r
r
o
e
l
r
s
e
g
0
i
s
3
t
e
E
1
r
6
)
1
IN
R
I
N
I
N
I
N
R
T
T
T
0
e
s
T
1
T
2
T
3
/
e
s
i
m
i
m
i
r
i
i
n
v
n
n
r
v
r
r
t
e
t
e
t
e
S
e
X
Y
e
r
r
(
r
r
r
(
n
n
u
D
u
u
i
a
D
t
e
t
e
p
o
p
p
l
o
r
r
t
t
t
I
/
r
r
e
n
e
e
O
n
u
u
n
o
n
n
2
i
o
t
p
t
p
t
a
t
a
a
b
w
b
b
n
w
e
e
l
r
l
l
t
r
e
i
e
e
e
i
a
a
e
b
b
r
t
e
b
b
b
i
t
“
i
t
i
t
u
“
l
e
l
e
e
d
r
r
e
d
i
i
t
1
”
t
o
t
h
i
s
b
i
t
.
)
r
p
1
t
”
b
b
i
i
e
t
o
t
t
n
a
t
h
b
i
l
s
e
b
b
i
i
t
.
e
e
e
t
)
n
n
s
0
In
(I
C
t
e
O
r
r
N
u
p
2
t
:
c
o
a
n
d
t
r
r
o
e
l
s
r
s
e
g
0
i
s
3
t
e
F
1
r
6
)
2
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
AD converter interrupt enable bit
Not used (returns
“
0
”
when read)
(Do not write
“
1
”
to this bit.)
:
I
n
t
e
r
r
u
p
t
s
d
i
1
:
I
n
t
e
r
r
u
p
t
s
e
n
0
s
a
a
b
b
l
e
e
d
d
l
d
0
0
1
:
:
I
I
n
n
t
t
e
e
r
r
r
r
u
u
p
p
t
t
s
s
d
e
i
n
s
a
a
b
b
l
e
e
d
d
l