參數(shù)資料
型號(hào)： DT28F160S3-100
廠商： INTEL CORP
元件分類： DRAM
英文描述： 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述： 2M X 8 FLASH 2.7V PROM, 100 ns, PDSO56
封裝： 16 X 23.70 MM, SSOP-56
文件頁(yè)數(shù)： 41/52頁(yè)
文件大小： 1262K
代理商： DT28F160S3-100
E
6.2.1
28F160S3, 28F320S3
41
ADVANCE INFORMATION
CAPACITANCE
Table 18. Capacitance
(1)
, T
A
= +25°C, f = 1 MHz
Symbol
Parameter
Typ
Max
Unit
Condition
C
IN
Input Capacitance
6
8
pF
V
IN
= 0.0V
C
OUT
Output Capacitance
8
12
pF
V
OUT
= 0.0V
NOTE:
1.
Sampled, not 100% tested.
6.2.2
AC INPUT/OUTPUT TEST CONDITIONS
TEST POINTS
INPUT
OUTPUT
1.35
2.7
0.0
1.35
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for V
CC
= 2.7V
–3.6V
TEST POINTS
INPUT
OUTPUT
1.5
3.0
0.0
1.5
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Input/Output Reference Waveform for V
CC
= 3.3V ± 0.3V
(High Speed Testing Configuration)
DEVICE
UNDER
TEST
1.3V
1N914
C
L
OUT
R = 3.3 k
C Includes Jig
Capacitance
Figure 16. Transient Equivalent Testing
Load Circuit
Test Configuration Capacitance Loading Value
Test Configuration
C
L
(pF)
V
CC
= 3.3V
±
0.3V, 2.7V to 3.6V
50
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