參數(shù)資料
型號： DSP56F807VF80
廠商： Freescale Semiconductor
文件頁數(shù)： 3/60頁
文件大?。?/td> 0K
描述： IC DSP 80MHZ 60K FLASH 160-BGA
標(biāo)準(zhǔn)包裝： 126
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 80MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 136KB（68K x 16）
程序存儲器類型： 閃存
RAM 容量： 6K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 160-BGA
包裝： 托盤
Clock and Phase Locked Loop Signals
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
11
2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Table 2-5 PLL and Clock
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
EXTAL
Input
External Crystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.4.
1
XTAL
Input/
Output
Chip-driven
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information, please
refer to Section 3.4.
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.4.2.
1
CLKO
Output
Chip-driven
Clock Output—This pin outputs a buffered clock signal. By programming
the CLKOSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user
can select between outputting a version of the signal applied to XTAL and
a version of the device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Table 2-6 Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
A0–A5
Output
Tri-stated
Address Bus—A0–A5 specify the address for external Program or
Data memory accesses.
2
A6–A7
GPIOE2-
GPIOE3
Output
Input/O
utput
Tri-stated
Input
Address Bus—A6–A7 specify the address for external Program or
Data memory accesses.
Port E GPIO—These two General Purpose I/O (GPIO) pins can
individually be programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15
GPIOA0-
GPIOA7
Output
Input/O
utput
Tri-stated
Input
Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F807VF80E 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F807VF80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC
DSP56F807VF80J 制造商:Freescale Semiconductor 功能描述:DSP 16BIT - Trays
DSP56F826 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F826-827UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor Users Manual
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