參數(shù)資料
型號(hào): DSP56F807VF80
廠商: Freescale Semiconductor
文件頁數(shù): 18/60頁
文件大?。?/td> 0K
描述: IC DSP 80MHZ 60K FLASH 160-BGA
標(biāo)準(zhǔn)包裝: 126
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 136KB(68K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 160-BGA
包裝: 托盤
AC Electrical Characteristics
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
25
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-14)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the V
IL and VIH levels specified in the DC Characteristics
table. In Figure 3-2 the levels of V
IH and VIL for an input signal are shown.
Figure 3-2 Input Signal Measurement References
Figure 3-3 shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
0
50
100
200
250
10
20
30
40
50
60
70
80
Freq. (MHz)
IDD
(mA)
150
IDD Digital
IDD Analog
IDD Total
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low
High
90%
50%
10%
Rise Time
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