參數(shù)資料
型號: DSP56F807VF80
廠商: Freescale Semiconductor
文件頁數(shù): 27/60頁
文件大?。?/td> 0K
描述: IC DSP 80MHZ 60K FLASH 160-BGA
標(biāo)準(zhǔn)包裝: 126
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 160-BGA
包裝: 托盤
External Bus Asynchronous Timing
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
33
3.5 External Bus Asynchronous Timing
Table 3-10 External Bus Asynchronous Timing1,2
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
Address Valid to WR Asserted
tAWR
6.5
ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR
7.5
(T*WS)+7.5
ns
WR Asserted to D0–D15 Out Valid
tWRD
—T + 4.2
ns
Data Out Hold Time from WR Deasserted
tDOH
4.8
ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS
2.2
(T*WS)+6.4
ns
RD Deasserted to Address Not Valid
tRDA
0—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
18.7
(T*WS) + 18.7
ns
Input Data Hold to RD Deasserted
tDRD
0—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
tRD
19
(T*WS)+19
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD
1
(T*WS)+1
ns
Address Valid to RD Asserted
tARDA
-4.4
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD
2.4
(T*WS) + 2.4
ns
WR Deasserted to RD Asserted
tWRRD
6.8
ns
RD Deasserted to RD Asserted
tRDRD
0—
ns
WR Deasserted to WR Asserted
tWRWR
14.1
ns
RD Deasserted to WR Asserted
tRDWR
12.8
ns
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