參數(shù)資料
型號: DSP56F805FV80E
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 12/56頁
文件大小: 415K
代理商: DSP56F805FV80E
56F805
Technical Data, Rev. 15
12
Freescale Semiconductor
Table 2-7 Data Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
16
D0–D15
Input/O
utput
Tri-stated
Data Bus
— D0–D15 specify the data for external Program or
Data memory accesses. D0–D15 are tri-stated when the external
bus is inactive. Internal pullups may be active.
Table 2-8 Bus Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
PS
Output
Tri-stated
Program Memory Select
—PS is asserted low for external
Program memory access.
1
DS
Output
Tri-stated
Data Memory Select
—DS is asserted low for external Data
memory access.
1
WR
Output
Tri-stated
Write Enable
—WR is asserted during external memory write
cycles. When WR is asserted low, pins D0–D15 become
outputs and the device puts data on the bus. When WR is
deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15,
PS, and DS pins. WR can be connected directly to the WE pin
of a Static RAM.
1
RD
Output
Tri-stated
Read Enable
—RD is asserted during external memory read
cycles. When RD is asserted low, pins D0–D15 become inputs
and an external device is enabled onto the device’s data bus.
When RD is deasserted high, the external data is latched
inside the device. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to
the OE pin of a Static RAM or ROM.
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