- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377001 > DSP56F805FV80E (飛思卡爾半導體(中國)有限公司) 16-bit Digital Signal Controllers PDF資料下載
參數(shù)資料
| 型號： | DSP56F805FV80E |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 11/56頁 |
| 文件大?。?/td> | 415K |
| 代理商： | DSP56F805FV80E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
Clock and Phase Locked Loop Signals
56F805 Technical Data, Rev. 15
Freescale Semiconductor
11
2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Table 2-5 PLL and Clock
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
EXTAL
Input
Input
External Crystal Oscillator Input
—This input should be
connected to an 8MHz external crystal or ceramic resonator. For
more information, please refer to
Section 3.5
.
1
XTAL
Input/O
utput
Chip-driven
Crystal Oscillator Output
—This output should be connected to
an 8MHz external crystal or ceramic resonator. For more
information, please refer to
Section 3.5
.
This pin can also be connected to an external clock source. For
more information, please refer to
Section 3.5.3
.
1
CLKO
Output
Chip-driven
Clock Output
—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Table 2-6 Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
A0–A5
Output
Tri-stated
Address Bus
—A0–A5 specify the address for external
Program or Data memory accesses.
2
A6–A7
GPIOE2
–
GPIOE3
Output
Input/O
utput
Tri-stated
Input
Address Bus
—A6–A7 specify the address for external
Program or Data memory accesses.
Port E GPIO
—These two General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15
GPIOA0
–
GPIOA7
Output
Input/O
utput
Tri-stated
Input
Address Bus
—A8–A15 specify the address for external
Program or Data memory accesses.
Port A GPIO
—These eight General Purpose I/O (GPIO) pins
can be individually be programmed as input or output pins.
After reset, the default state is Address Bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56F805 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP56F807PY80E | 16-bit Digital Signal Controllers |
| DSP56F807VF80E | 16-bit Digital Signal Controllers |
| DSP56F807 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP56F826BU80 | 16-bit Digital Signal Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F805FV80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F805FV80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP144 3.6V |
| DSP56F805PB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F805 16-Bit Hybrid Controller Product Brief |
| DSP56F807 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F807 16-bit Hybrid Processor |
| DSP56F807EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F807 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
發(fā)布緊急采購，3分鐘左右您將得到回復。