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參數(shù)資料

型號：	DSP56321VL275
廠商：	飛思卡爾半導體(中國)有限公司
元件分類：	數(shù)字信號處理
英文描述：	24-Bit Digital Signal Processor
中文描述：	24位數(shù)字信號處理器
文件頁數(shù)：	43/84頁
文件大小：	898K
代理商：	DSP56321VL275

AC Electrical Characteristics

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor

2-23

2.4.8

ESSI0/ESSI1 Timing

Table 2-12.

ESSI Timings

No.

Characteristics

4, 6

Symbol

Expression

200 MHz

220 MHz

240 MHz

275 MHz

Cond-

ition

5

Unit

Min Max Min Max Min Max Min Max

430 Clock cycle

1

T

ECCX

T

ECCI

6

×

T

C

8

×

T

C

30.0

40.0

—

—

27.3

36.6

—

—

25.0

33.3

—

—

21.5

25.0

—

—

x ck

i ck

ns

ns

431 Clock high period

For internal clock

For external clock

T

ECCX

/2 – 3.7

T

ECCI

/2 – 10.0

11.3

10.0

—

—

9.9

8.2

—

—

8.8

6.7

—

—

7.21

2.5

—

—

ns

ns

432 Clock low period

For internal clock

For external clock

T

ECCX

/2 – 3.7

T

ECCI

/2

10.0

11.3

10.0

—

—

9.9

8.2

—

—

8.8

6.7

—

—

7.21

2.5

—

—

ns

ns

433 RXC rising edge to FSR out (bit-length)

high

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck a

ns

434 RXC rising edge to FSR out (bit-length)

low

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck a

ns

435 RXC rising edge to FSR out (word-

length-relative) high

2

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck a

ns

436 RXC rising edge to FSR out (word-

length-relative) low

2

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck a

ns

437 RXC rising edge to FSR out (word-

length) high

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck a

ns

438 RXC rising edge to FSR out (word-

length) low

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck a

ns

439 Data in setup time before RXC (SCK in

Synchronous mode) falling edge

5.0

10.0

—

—

5.0

10.0

—

—

5.0

10.0

—

—

5.0

10.0

—

—

x ck

i ck

ns

440 Data in hold time after RXC falling edge

3.8

5.0

—

—

3.8

5.0

—

—

3.8

5.0

—

—

3.8

5.0

—

—

x ck

i ck

ns

441 FSR input (bl, wr) high before RXC

falling edge

2

5.0

10.0

—

—

5.0

10.0

—

—

5.0

10.0

—

—

5.0

10.0

—

—

x ck

i ck a

ns

442 FSR input (wl) high before RXC falling

edge

5.0

10.0

—

—

5.0

10.0

—

—

5.0

10.0

—

—

5.0

10.0

—

—

x ck

i ck a

ns

443 FSR input hold time after RXC falling

edge

3.8

5.0

—

—

3.8

5.0

—

—

3.8

5.0

—

—

3.8

5.0

—

—

x ck

i ck a

ns

444 Flags input setup before RXC falling

edge

5.0

10.0

—

—

5.0

10.0

—

—

5.0

10.0

—

—

5.0

10.0

—

—

x ck

i ck s

ns

445 Flags input hold time after RXC falling

edge

3.8

5.0

—

—

3.8

5.0

—

—

3.8

5.0

—

—

3.8

5.0

—

—

x ck

i ck s

ns

446 TXC rising edge to FST out (bit-length)

high

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck

ns

447 TXC rising edge to FST out (bit-length)

low

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck

ns

448 TXC rising edge to FST out (word-

length-relative) high

2

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck

ns

449 TXC rising edge to FST out (word-

length-relative) low

2

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck

ns

450 TXC rising edge to FST out (word-

length) high

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

—

—

12.5

8.3

x ck

i ck

ns

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