DRAM Page Mode Timings, Four " />
參數(shù)資料
型號： DSP56303AG100R2
廠商： Freescale Semiconductor
文件頁數(shù)： 40/108頁
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 144-LQFP
標準包裝： 500
系列： DSP563xx
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 100MHz
非易失內存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應商設備封裝： 144-LQFP（20x20）
包裝： 帶卷 (TR)
AC Electrical Characteristics
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
2-17
Table 2-10.
DRAM Page Mode Timings, Four Wait States1,2,3
No.
Characteristics
Symbol
Expression4
100 MHz
Unit
Min
Max
131
Page mode cycle time for two consecutive accesses of the same
direction
Page mode cycle time for mixed (read and write) accesses
tPC
5
× TC
4.5
× TC
50.0
45.0
—
ns
132
CAS assertion to data valid (read)
tCAC
2.75
× TC 5.7
—
21.8
ns
133
Column address valid to data valid (read)
tAA
3.75
× T
C 5.7
—
31.8
ns
134
CAS deassertion to data not valid (read hold time)
tOFF
0.0
—
ns
135
Last CAS assertion to RAS deassertion
tRSH
3.5
× TC 4.0
31.0
—
ns
136
Previous CAS deassertion to RAS deassertion
tRHCP
6
× T
C 4.0
56.0
—
ns
137
CAS assertion pulse width
tCAS
2.5
× TC 4.0
21.0
—
ns
138
Last CAS deassertion to RAS assertion
5
BRW[1–0] = 00, 01—Not applicable
BRW[1–0] = 10
BRW[1–0] = 11
tCRP
—
5.25
× TC 6.0
7.25
× TC 6.0
—
46.5
66.5
—
ns
139
CAS deassertion pulse width
tCP
2
× T
C 4.0
16.0
—
ns
140
Column address valid to CAS assertion
tASC
TC 4.0
6.0
—
ns
141
CAS assertion to column address not valid
tCAH
3.5
× TC 4.0
31.0
—
ns
142
Last column address valid to RAS deassertion
tRAL
5
× T
C 4.0
46.0
—
ns
143
WR deassertion to CAS assertion
tRCS
1.25
× TC 4.0
8.5
—
ns
144
CAS deassertion to WR assertion
tRCH
1.25
× TC – 3.7
8.8
—
ns
145
CAS assertion to WR deassertion
tWCH
3.25
× T
C 4.2
28.3
—
ns
146
WR assertion pulse width
tWP
4.5
× TC 4.5
40.5
—
ns
147
Last WR assertion to RAS deassertion
tRWL
4.75
× TC 4.3
43.2
—
ns
148
WR assertion to CAS deassertion
tCWL
3.75
× T
C 4.3
33.2
—
ns
149
Data valid to CAS assertion (write)
tDS
0.5
× TC – 4.5
0.5
—
ns
150
CAS assertion to data not valid (write)
tDH
3.5
× TC 4.0
31.0
—
ns
151
WR assertion to CAS assertion
tWCS
1.25
× T
C 4.3
8.2
—
ns
152
Last RD assertion to RAS deassertion
tROH
4.5
× TC 4.0
41.0
—
ns
153
RD assertion to data valid
tGA
3.25
× TC 5.7
—
26.8
ns
154
RD deassertion to data not valid6
tGZ
0.0
—
ns
155
WR assertion to data active
0.75
× TC – 1.5
6.0
—
ns
156
WR deassertion to data high impedance
0.25
× TC
—2.5
ns
Notes:
1.
The number of wait states for Page mode access is specified in the DRAM Control Register.
2.
The refresh period is specified in the DRAM Control Register.
3.
The asynchronous delays specified in the expressions are valid for the DSP56303.
4.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 3 ×
TC for read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum value
listed, as appropriate.
5.
BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
6.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
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