參數(shù)資料
型號(hào): DSP56303AG100R2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 36/108頁(yè)
文件大?。?/td> 0K
描述: IC DSP 24BIT 100MHZ 144-LQFP
標(biāo)準(zhǔn)包裝: 500
系列: DSP563xx
類(lèi)型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時(shí)鐘速率: 100MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 帶卷 (TR)
AC Electrical Characteristics
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
2-13
111
WR deassertion to data high impedance
0.25
× TC + 0.2
[1
≤WS ≤3]
1.25
× TC + 0.2
[4
≤WS ≤7]
2.25
× TC + 0.2
[WS > 8]
2.7
12.7
22.7
ns
112
Previous RD deassertion to data active (write)
1.25
× TC – 4.0
[1
≤WS ≤3]
2.25
× TC – 4.0
[4
≤WS ≤7]
3.25
× T
C – 4.0
[WS > 8]
8.5
18.5
28.5
ns
113
RD deassertion time
0.75
× T
C 4.0
[1
≤WS ≤3]
1.75
× TC 4.0
[4
≤WS ≤7]
2.75
× TC 4.0
[WS
≥ 8]
3.5
13.5
23.5
ns
114
WR deassertion time
0.5
× TC 4.0
[WS = 1]
TC 4.0
[2
≤WS ≤3]
2.5
× TC 4.0
[4
≤WS ≤7]
3.5
× TC 4.0
[WS
≥ 8]
1.0
6.0
21.0
31.0
ns
115
Address valid to RD assertion
0.5
× TC 4.0
1.0
ns
116
RD assertion pulse width
(WS + 0.25)
× T
C 4.0
8.5
ns
117
RD deassertion to address not valid
0.25
× TC 2.0
[1
≤WS ≤3]
1.25
× TC 2.0
[4
≤WS ≤7]
2.25
× T
C 2.0
[WS
≥ 8]
0.5
10.5
20.5
ns
118
TA setup before RD or WR deassertion4
—0.25
× T
C + 2.0
4.5
ns
119
TA hold after RD or WR deassertion
0
ns
Notes:
1.
WS is the number of wait states specified in the BCR. An expression is used to compute the number listed as the minimum or
maximum value, as appropriate.
2.
Timings 100, 107 are guaranteed by design, not tested.
3.
All timings for 100 MHz are measured from 0.5
× Vcc to 0.5 × Vcc.
4.
Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.
5.
VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100°C, CL = 50 pF
Table 2-8.
SRAM Read and Write Accesses (Continued)
No.
Characteristics
Symbol
Expression1
100 MHz
Unit
Min
Max
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