參數(shù)資料
型號： DS89C420-QCL
英文描述： Ultra-High-Speed Microcontroller
中文描述： 超高速微控制器
文件頁數(shù)： 41/59頁
文件大?。?/td> 539K
代理商： DS89C420-QCL
DS89C420
41 of 59
switchback if the SWB is set. Note that the serial port activity, as related to the switchback, is
independent of the serial port interrupt relationship. Any attempt to change the clock divider to the
divide-by-1024 mode while the serial port is either transmitting or receiving has no effect, leaving the
clock control in the divide-by-1 mode. Note also that the switchback interrupt relationship requires that
the respective external interrupt source is allowed to actually generate an interrupt as defined by the
priority of the interrupt and the state of the nested interrupts, before the switchback can actually occur. An
interrupt by the serial port is not required, nor is the setting of serial port enable. Disabling external
interrupts and serial port receive/transmission mode disable the automatic switchback mode. Clearing the
SWB bit also disables the switchback, and all interrupt and serial port controls of the clock divider are
disabled. All other clock modes ignore the switchback relationship and are unaffected by interrupts and
serial port activity.
The basic divide-by-12 mode for the timers (TxMH, TxM = 00b), as well as the divide-by-32 and 64 for
mode 2 on the serial ports, are maintained when running the processor with the oscillator divide ratio of
0.25, 0.5, and 1. Serial ports and timers track the oscillator cycles per machine cycle when the higher
divide ratio of 1024 is selected, and require the switchback function to automatically return to the
divide-by-1 mode for proper operation when a qualified event occurs. Table 15 summarizes the effect of
clock mode on timer operation.
It is possible to enable a receive function on a serial port when incoming data is not present and then
change to the higher divide ratio. An inactive serial port receive/transmit mode requires the receive input
pin to remain high and all outgoing transmissions to be completed. During this inactive receive mode it is
possible to change the clock-divide control bits from a divide-by-1 to a 1024 divide ratio. In the case
when the serial port is being used to receive or transmit data it is very important to validate an attempted
change in the clock-divide control bits (read CD1 and CD0 to verify write was allowed) before
proceeding with low-power program functions.
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