參數(shù)資料
型號： DS89C420-QCL
英文描述： Ultra-High-Speed Microcontroller
中文描述： 超高速微控制器
文件頁數(shù)： 25/59頁
文件大?。?/td> 539K
代理商： DS89C420-QCL
DS89C420
25 of 59
Page Mode, External Memory Cycle
Page mode retains the basic circuitry requirement for original 8051 external memory interface, but alters
the configuration of P0 and P2 for the purposes of address output and data I/O during external memory
cycles. Additionally, the functions of ALE and
PSEN
are altered to support this mode of operation.
Page mode is enabled by setting the PAGEE (ACON.7) bit to a logic 1. Clearing the PAGEE bit to a
logic 0 disables the page mode and the external bus structure defaults to the original 8051 expanded bus
configuration (non-page mode). The DS89C420 supports page mode in two external bus structures. The
logic value of the page mode select bits in the ACON register determines the external bus structure and
the basic memory cycle in the number of system clocks. Table 7 summarizes this option. The first three
selections use the same bus structure but with a different memory cycle time. Setting the select bits to 11b
selects another bus structure. Write access to the ACON register requires a timed access.
Table 7. Page Mode Select
CLOCKS PER MEMORY CYCLE
PAGE HIT
PAGES1:PAGES0
PAGE MISS
EXTERNAL BUS STRUCTURE
00
1
2
P0: Primary data bus.
P2: Primary address bus, multiplexing both
the upper byte and lower byte of the address.
P0: Primary data bus.
P2: Primary address bus, multiplexing both
the upper byte and lower byte of the address.
P0: Primary data bus.
P2: Primary address bus, multiplexing both
the upper byte and lower byte of the address.
01
2
4
10
4
8
11
2
4
P0: Lower address byte.
P2: The upper address byte is multiplexed
with the data byte.
Note:
This setting affects external code
fetches only; accessing the external data
memory requires 4 clock cycles, regardless
of page hit or miss.
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