參數(shù)資料
型號(hào)： DS89C420-QCL
英文描述： Ultra-High-Speed Microcontroller
中文描述： 超高速微控制器
文件頁(yè)數(shù)： 37/59頁(yè)
文件大?。?/td> 539K
代理商： DS89C420-QCL
DS89C420
37 of 59
Power Management and Clock-Divide Control
The DS89C420 incorporates power management features that monitor the power-supply voltage levels
and support low-power operation with three power-saving modes. Such features include a bandgap
voltage monitor, watchdog timer, selectable internal ring oscillator, and programmable system clock
speed. The SFRs that provide control and application software access are the watchdog control
(WDCON, D8h), extended interrupt enable (EIE, E8h), extended interrupt flag (EXIF, 91h), and power
control (PCON, 87h) registers.
System Clock-Divide Control
The programmable clock-divide control bits (CD1 and CD0) provide the processor with the ability to
adapt to different crystals and also to slow the system clocks providing lower power operation when
required. An on-chip crystal multiplier allows the DS89C420 to operate at two or four times the crystal
frequency by setting the 4X/
X
2
bit and is enabled by setting the CTM bit to a logic 1. An additional
circuit provides a clock source at divide-by-1024. When used with a 7.372MHz crystal, for example, the
processor executes machine cycle in times ranging from 33.9ns (divide-by-0.25) to 138.9μs (multiply by
1024), and maintains a highly accurate serial port baud rate while allowing the use of more cost-effective,
lower-frequency crystals. Although the clock-divide control bits can be written at any time, certain
hardware features have been provided to enhance the use of these clock controls to guarantee proper
serial port operation, and also to allow for a high-speed response to an external interrupt. The 01b setting
of CD1 and CD0 is reserved, and has the same effect as the 10b setting, which forces the system clock
into a divide by 1 mode. The DS89C420 defaults to divide-by-1 clock mode on all forms of reset.
When programmed to the divide-by-1024 mode, and the switchback bit (PMR.5:SWB) is also set, the
system forces the clock-divide control bits to reset automatically to the divide-by-1 mode whenever the
system has detected externally enabled interrupts.
The oscillator divide ratios of 0.25, 0.5, and 1 are also used to provide standard baud-rate generation for
the serial ports through a forced divide-by-12 input clock (TxMH, TxM = 00b, x = 1, 2, or 3) to the
timers.
When in divide-by-1024 mode, in order to allow a quick response to incoming data on a serial port, the
system uses the switchback mode to automatically revert to divide-by-1 mode whenever a start bit is
detected. This automatic switchback is only enabled during divide-by-1024 mode, and all other clock
modes are unaffected by interrupts and serial port activity. See
Power Management Mode
for more
details.
Use of the divide-by-0.25 or 0.5 options through the clock-divide control bits requires that the crystal
multiplier be enabled and the specific system-clock-multiply value be established by the 4X/
X
PMR register. The multiplier is enabled through the CTM (PMR.4) bit but cannot be automatically
selected until a startup delay has been established through the CKRY bit in the status register. The
4X/
X
2
bit can only be altered when the CTM bit is cleared to a logic 0. This prevents the system from
changing the multiplier until the system has moved back to the divide by 1 mode and the multiplier has
been disabled through the CTM bit. The CTM bit can only be altered when the CD1 and CD0 bits are set
to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to a logic 1 from a previous
logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup timeout in
2
bit in the
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