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參數(shù)資料
| 型號： | DS87C550 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | EPROM High-Speed Micro with A/D and PWM(帶 A/D 和 PWM的EPROM/ROM高速微控制器) |
| 中文描述： | 存儲器高速微與A / D及PWM（帶A / D轉換和脈寬調制的存儲器/ ROM的高速微控制器） |
| 文件頁數(shù)： | 9/27頁 |
| 文件大?。?/td> | 119K |
| 代理商： | DS87C550 |
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APPLICATION NOTE 78
030998 9/27
Serial Port Activity and PMM
Because the function of PMM is to change the internal
clock frequency of the DS87C5x0, timing–dependent
peripherals such as the serial ports can be affected. The
user must be sure that the serial ports are not receiving
or transmitting when switching into PMM. The simplest
way to do this is to interrogate the serial port activity bits
in the Status register (STATUS.3–0).
During a receive operation, the falling edge of the start
bit will activate the switchback, if enabled. The serial
port activity monitor bit will be set, and the serial port will
then check for a valid start bit. If the start bit is received,
the serial reception will continue normally, and generate
an interrupt when the entire word is received, if enabled.
To minimize power consumption, PMM may be enabled
again at the start of the serial port interrupt service rou-
tine if no further processing is needed in divide by 4
mode.
It is possible to experience a “spurious” switchback
caused by a noisy serial port. The DS87C5x0 initiates a
switchback on the first falling edge on the RX pin, and
begins looking for a valid start bit. If a valid start bit is not
received, the system will abort the serial activity, clear-
ing the activity bit, and no serial port interrupt will be
executed. The switchback has already been initiated,
however, and the device is now operating at full speed.
To return the device to PMM, it will be necessary for the
user to manually reset the clock rate divider bits.
The code fragment shown in Figure 5 illustrates one
possible test for an invalid return to divide by 4 mode.
This test can be inserted into the main code loop where it
will be periodically executed, or it could be made part of
a timer interrupt routine. If no interrupts or serial ports
are active, it is likely that the device should be in PMM,
not divide by 4 mode. This code should be customized
according to the specific configuration, i.e. if a PMM
should be allowed in a low priority interrupt, then mask
out that bit when testing the Status register.
INVALID SWITCHBACK TEST EXAMPLE
Figure 5
MODETEST: PUSH A ;Save the current value of the accumulator.
MOV A, PMR ;Move the data to a bit–addressable register.
JB E7, PMM_ON ;If bit 7 is set, device is already in PMM.
CHK_STAT: MOV A, STATUS ;Check status register for active interrupts.
AND A, #0EFh ;Check for user–defined activity.
JNZ CHK_STAT ;If activity, loop until complete.
. ;(Code can either loop until the condition
. ; clears or abort attempt to reenter PMM.)
ENA_PMM: OR PMR, #0C0h ;Status okay for return to PMM. Set Clock Rate
; Divider bits (example shows return to PMM2)
PMM_ON: POP A ;Restore accumulator.
Multiprocessor Communications in PMM
The effectiveness of PMM and the switchback feature is
affected if multiprocessor communications protocols
are used. The DS87C5x0 includes features that will
support multiple processors on the same serial port. In
serial port modes 2 and 3 it is possible to use the SM2
flag (SCON0.5 or SCON1.5) to signify that the received
byte is an address. The slave address recognition regis-
ters (SADDR0;A9h, SADDR1;AAh, SADEN0;B9h,
SADEN1;BAh) can be programmed to ignore a trans-
mission (not cause a receiver interrupt) when a received
address does not match a user defined pattern.
The implication of multiprocessor communications for
power management is that a switchback is generated by
the detection of the first falling edge on a serial port, not
the generation of a valid interrupt. As a result, an invalid
address which should be ignored by a particular proces-
sor will still generate a switchback. Normally, the part
could be returned to PMM at the start of the serial port
interrupt service routine. Unfortunately, in the above
mentioned case no interrupt will be generated. To allevi-
ate this problem, one should avoid using a multiproces-
sor communication scheme in conjunction with PMM. If
the system power considerations will allow for an occa-
sional erroneous switchback, the polling scheme shown
in Figure 5 can be used to place the device back into
PMM.
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| DS87C550-FCL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
| DS87C550-FNL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
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| DS87C550-QCL+ | 功能描述:IC MCU EPROM ADC/PWM HS 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:87C 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:260 系列:73S12xx 核心處理器:80515 芯體尺寸:8-位 速度:24MHz 連通性:I²C，智能卡，UART/USART，USB 外圍設備:LED，POR，WDT 輸入/輸出數(shù):9 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-VFQFN 裸露焊盤 包裝:管件 |
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