
APPLICATION NOTE 78
030998 5/27
Note that changing the clock divisor, either manually or
through a switchback, will not affect Timed Access pro-
cedures. Timed Access operates in relation to internal
machine cycles, not an absolute time reference.
TIMERS AND PMM
Timers 0, 1, and 2 will default on power–up to a 12 exter-
nal clocks per timer tick to remain compatible with the
original 8051/8032 specifications. The timers can be
individually configured to run at a rate of four external
clocks per timer tick when the device is operating in
divide by 4 mode by setting the relevant bits in the Clock
Control Register (CKCON;8Eh). During PMM timers 0,
1, and 2 operate at correspondingly reduced clock
rates, because the timers derive their time base from the
internal clock. This will also affect the operation of the
serial ports in PMM as the timers are used to generate
baud rates. Table 2 shows the effect of the clock divide
rate on timer operation.
EFFECT OF CLOCK MODES ON TIMER OPERATION
Table 2
CD1
CD0
OSC.
CYCLES PER
MACHINE
CYCLE
OSC. CYCLES
PER TIMER
0/1/2 CLOCK
OSC. CYCLES
PER TIMER 2
CLOCK, BAUD
RATE GEN.
OSC. CYCLES
PER SERIAL
PORT CLOCK
MODE 0
OSC. CYCLES PER
SERIAL PORT
CLOCK MODE 2
TxM=1
TxM=0
T2M=1
T2M=0
SM2=0
SM2=1
SMOD=0
SMOD=1
0
0
Reserved
0
1
4
12
4
2
2
12
4
64
32
1
0
64 (PMM1)
192
64
32
32
192
64
1024
512
1
1
1024 (PMM2)
3072
1024
512
512
3072
1024
16,384
8192
The watchdog timer runs off the same time base as the
internal clocks; i.e. if the device is in PMM1, the watch-
dog will also be running in a divide by 64 mode. This
keeps the watchdog timer synchronized with the opera-
tion of the processor when switching between PMM and
divide by 4 mode. Applications that use the watchdog
timer as an additional timer should take this into account
if PMM is used.
The real time clock is independent of the PMM setting. It
uses the external 32 KHz crystal as its reference, and
can be accessed in any mode.
MANUALLY EXITING PMM
In addition to the switchback feature, it is also possible
to manually exit a PMM by configuring the clock divider
rate bits. Entry to or exit from either PMM can only be via
the divide by 4 mode, and attempts to execute an illegal
speed change will be ignored and the bits will remain
unchanged. If a timing–dependent operation may be in
progress, the Status register (STATUS;C5h) should be
interrogated to determine if it has been completed
before switching out of or into PMM.
RESET SENSITIVITY IN PMM
While in PMM, the method used to detect an external
reset pulse differs from that used in divide by 4 mode. In
divide by 4 mode, (and standard 8051 architecture) a
reset must be high for two machine cycles to be
detected. If this were true in PMM, reset would have to
be asserted for a minimum of 128 or 2048 clock cycles.
To avoid this, devices operating in PMM employ a posi-
tive edge–detect sensor, rather than a one machine
cycle qualification to detect a reset signal. This means
that devices which use PMM are more susceptible to
noise and additional care must be taken to keep the
reset signal noise–free.
SWITCHBACK FEATURE
Description
The switchback feature allows the user to quickly
restore the DS87C5x0 to a higher speed when an event
occurs. When enabled, a qualified event causes the
device to automatically switch from divide by 64 (PMM1)
or divide by 1024 (PMM2) to divide by 4 operation with-
out software intervention. This allows the device to